diff options
author | Clifford Wolf <clifford@clifford.at> | 2014-07-26 20:12:50 +0200 |
---|---|---|
committer | Clifford Wolf <clifford@clifford.at> | 2014-07-26 20:12:50 +0200 |
commit | 946ddff9cef3ea0b4dad8664319fb13074133775 (patch) | |
tree | e35f5ebe3cd76a8e10fe945872e32c2ed3a7d815 /passes/abc/abc.cc | |
parent | d49dec1f861ce11a87c48cc21c8edc1755802a5f (diff) | |
download | yosys-946ddff9cef3ea0b4dad8664319fb13074133775.tar.gz yosys-946ddff9cef3ea0b4dad8664319fb13074133775.tar.bz2 yosys-946ddff9cef3ea0b4dad8664319fb13074133775.zip |
Changed a lot of code to the new RTLIL::Wire constructors
Diffstat (limited to 'passes/abc/abc.cc')
-rw-r--r-- | passes/abc/abc.cc | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index 4d9a6c136..41cfe88f6 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -313,11 +313,9 @@ static void handle_loops() continue; } - RTLIL::Wire *wire = new RTLIL::Wire; std::stringstream sstr; sstr << "$abcloop$" << (RTLIL::autoidx++); - wire->name = sstr.str(); - module->wires[wire->name] = wire; + RTLIL::Wire *wire = module->addWire(sstr.str()); bool first_line = true; for (int id2 : edges[id1]) { @@ -691,9 +689,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std log_error("ABC output file does not contain a module `netlist'.\n"); for (auto &it : mapped_mod->wires) { RTLIL::Wire *w = it.second; - RTLIL::Wire *wire = new RTLIL::Wire; - wire->name = remap_name(w->name); - module->wires[wire->name] = wire; + RTLIL::Wire *wire = module->addWire(remap_name(w->name)); design->select(module, wire); } |