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| author | Clifford Wolf <clifford@clifford.at> | 2015-10-13 14:21:20 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-10-13 14:21:20 +0200 |
| commit | f13e3873212fb4338ee3dd180cb9b0cd3d134935 (patch) | |
| tree | f2cfe06b4332859abb143fe4ed69f054de491522 /misc | |
| parent | 34f34be17c891ffb99ca76700634aeff9da76bde (diff) | |
| download | yosys-f13e3873212fb4338ee3dd180cb9b0cd3d134935.tar.gz yosys-f13e3873212fb4338ee3dd180cb9b0cd3d134935.tar.bz2 yosys-f13e3873212fb4338ee3dd180cb9b0cd3d134935.zip | |
SystemVerilog also has assume(), added implicit -D FORMAL
Diffstat (limited to 'misc')
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