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| author | Ruben Undheim <ruben.undheim@gmail.com> | 2018-10-18 21:27:04 +0200 |
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| committer | Ruben Undheim <ruben.undheim@gmail.com> | 2018-10-18 22:40:53 +0200 |
| commit | d5aac2650f9169b2b890854083c5502b84adf115 (patch) | |
| tree | 9a0ef937b730d4c0f7452b0ceedfb642c83908ab /misc | |
| parent | a25f370191707def4d50dd42e74dec4d097a6a22 (diff) | |
| download | yosys-d5aac2650f9169b2b890854083c5502b84adf115.tar.gz yosys-d5aac2650f9169b2b890854083c5502b84adf115.tar.bz2 yosys-d5aac2650f9169b2b890854083c5502b84adf115.zip | |
Basic test for checking correct synthesis of SystemVerilog interfaces
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