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| author | Clifford Wolf <clifford@clifford.at> | 2014-01-03 00:22:17 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-01-03 00:22:17 +0100 |
| commit | fb2bf934dc6d2c969906b350c9a1b09a972bfdd7 (patch) | |
| tree | ea47a664de2af51f09fe43f3040685438f5dd2ec /manual | |
| parent | 536e20bde159db3ad8c77aeb9001a8dddde884a8 (diff) | |
| download | yosys-fb2bf934dc6d2c969906b350c9a1b09a972bfdd7.tar.gz yosys-fb2bf934dc6d2c969906b350c9a1b09a972bfdd7.tar.bz2 yosys-fb2bf934dc6d2c969906b350c9a1b09a972bfdd7.zip | |
Added correct handling of $memwr priority
Diffstat (limited to 'manual')
| -rw-r--r-- | manual/CHAPTER_CellLib.tex | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex index 61713e74d..b84e1b30e 100644 --- a/manual/CHAPTER_CellLib.tex +++ b/manual/CHAPTER_CellLib.tex @@ -272,6 +272,9 @@ the \B{CLK} input is not used. \item \B{CLK\_POLARITY} \\ Clock is active on positive edge if this parameter has the value {\tt 1'b1} and on the negative edge if this parameter is {\tt 1'b0}. + +\item \B{PRIORITY} \\ +The cell with the higher integer value in this parameter wins a write conflict. \end{itemize} The HDL frontend models a memory using RTLIL::Memory objects and asynchronous |