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| author | Clifford Wolf <clifford@clifford.at> | 2014-08-15 14:11:40 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-08-15 14:11:40 +0200 |
| commit | f092b5014895dc5dc62b8103fcedf94cfa9f85a8 (patch) | |
| tree | 2f09add560746030249fe333e551de2f113bccdb /manual | |
| parent | bf486002d9a6d976b3d086700ccdcfb0fb70ba0b (diff) | |
| download | yosys-f092b5014895dc5dc62b8103fcedf94cfa9f85a8.tar.gz yosys-f092b5014895dc5dc62b8103fcedf94cfa9f85a8.tar.bz2 yosys-f092b5014895dc5dc62b8103fcedf94cfa9f85a8.zip | |
Renamed $_INV_ cell type to $_NOT_
Diffstat (limited to 'manual')
| -rw-r--r-- | manual/CHAPTER_CellLib.tex | 4 | ||||
| -rw-r--r-- | manual/CHAPTER_StateOfTheArt/simlib_yosys.v | 4 | ||||
| -rw-r--r-- | manual/PRESENTATION_ExSyn.tex | 2 | ||||
| -rw-r--r-- | manual/PRESENTATION_Prog.tex | 2 |
4 files changed, 6 insertions, 6 deletions
diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex index f05c1b7ad..ea4ae8d40 100644 --- a/manual/CHAPTER_CellLib.tex +++ b/manual/CHAPTER_CellLib.tex @@ -371,7 +371,7 @@ source tree. \begin{tabular}[t]{ll} Verilog & Cell Type \\ \hline -\lstinline[language=Verilog]; Y = ~A; & {\tt \$\_INV\_} \\ +\lstinline[language=Verilog]; Y = ~A; & {\tt \$\_NOT\_} \\ \lstinline[language=Verilog]; Y = A & B; & {\tt \$\_AND\_} \\ \lstinline[language=Verilog]; Y = A | B; & {\tt \$\_OR\_} \\ \lstinline[language=Verilog]; Y = A ^ B; & {\tt \$\_XOR\_} \\ @@ -398,7 +398,7 @@ $ClkEdge$ & $RstLvl$ & $RstVal$ & Cell Type \\ \end{table} Table~\ref{tab:CellLib_gates} lists all cell types used for gate level logic. The cell types -{\tt \$\_INV\_}, {\tt \$\_AND\_}, {\tt \$\_OR\_}, {\tt \$\_XOR\_} and {\tt \$\_MUX\_} +{\tt \$\_NOT\_}, {\tt \$\_AND\_}, {\tt \$\_OR\_}, {\tt \$\_XOR\_} and {\tt \$\_MUX\_} are used to model combinatorial logic. The cell types {\tt \$\_DFF\_N\_} and {\tt \$\_DFF\_P\_} represent d-type flip-flops. diff --git a/manual/CHAPTER_StateOfTheArt/simlib_yosys.v b/manual/CHAPTER_StateOfTheArt/simlib_yosys.v index a2df8f648..54c076614 100644 --- a/manual/CHAPTER_StateOfTheArt/simlib_yosys.v +++ b/manual/CHAPTER_StateOfTheArt/simlib_yosys.v @@ -20,12 +20,12 @@ * The internal logic cell simulation library. * * This verilog library contains simple simulation models for the internal - * logic cells (_INV_, _AND_, ...) that are generated by the default technology + * logic cells (_NOT_, _AND_, ...) that are generated by the default technology * mapper (see "stdcells.v" in this directory) and expected by the "abc" pass. * */ -module _INV_(A, Y); +module _NOT_(A, Y); input A; output Y; assign Y = ~A; diff --git a/manual/PRESENTATION_ExSyn.tex b/manual/PRESENTATION_ExSyn.tex index f68b6f984..803982295 100644 --- a/manual/PRESENTATION_ExSyn.tex +++ b/manual/PRESENTATION_ExSyn.tex @@ -367,7 +367,7 @@ to map all RTL cell types to a generic library of built-in logic gates and regis \bigskip \begin{block}{The built-in logic gate types are:} -{\tt \$\_INV\_ \$\_AND\_ \$\_OR\_ \$\_XOR\_ \$\_MUX\_} +{\tt \$\_NOT\_ \$\_AND\_ \$\_OR\_ \$\_XOR\_ \$\_MUX\_} \end{block} \bigskip diff --git a/manual/PRESENTATION_Prog.tex b/manual/PRESENTATION_Prog.tex index 3b2145444..4e9f4b21e 100644 --- a/manual/PRESENTATION_Prog.tex +++ b/manual/PRESENTATION_Prog.tex @@ -303,7 +303,7 @@ cell name from the internal cell library: $not $pos $bu0 $neg $and $or $xor $xnor $reduce_and $reduce_or $reduce_xor $reduce_xnor $reduce_bool $shl $shr $sshl $sshr $lt $le $eq $ne $eqx $nex $ge $gt $add $sub $mul $div $mod $pow $logic_not $logic_and $logic_or $mux $pmux $slice $concat $lut $assert $sr $dff -$dffsr $adff $dlatch $dlatchsr $memrd $memwr $mem $fsm $_INV_ $_AND_ $_OR_ $_XOR_ $_MUX_ $_SR_NN_ +$dffsr $adff $dlatch $dlatchsr $memrd $memwr $mem $fsm $_NOT_ $_AND_ $_OR_ $_XOR_ $_MUX_ $_SR_NN_ $_SR_NP_ $_SR_PN_ $_SR_PP_ $_DFF_N_ $_DFF_P_ $_DFF_NN0_ $_DFF_NN1_ $_DFF_NP0_ $_DFF_NP1_ $_DFF_PN0_ $_DFF_PN1_ $_DFF_PP0_ $_DFF_PP1_ $_DFFSR_NNN_ $_DFFSR_NNP_ $_DFFSR_NPN_ $_DFFSR_NPP_ $_DFFSR_PNN_ $_DFFSR_PNP_ $_DFFSR_PPN_ $_DFFSR_PPP_ $_DLATCH_N_ $_DLATCH_P_ $_DLATCHSR_NNN_ $_DLATCHSR_NNP_ |