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| author | Clifford Wolf <clifford@clifford.at> | 2019-01-07 10:07:28 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-01-07 10:07:28 +0100 |
| commit | f042559e9dbcc0738c6404903ac22da63cd27404 (patch) | |
| tree | ddb8488ee04dffd4fce9954ab2c2b32d6008d5a5 /manual | |
| parent | 8a63fc51d31bca50c3d08130c3271a288af1cf4b (diff) | |
| download | yosys-f042559e9dbcc0738c6404903ac22da63cd27404.tar.gz yosys-f042559e9dbcc0738c6404903ac22da63cd27404.tar.bz2 yosys-f042559e9dbcc0738c6404903ac22da63cd27404.zip | |
Fix typo in manual
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'manual')
| -rw-r--r-- | manual/CHAPTER_CellLib.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex index d40a600ed..e22664a82 100644 --- a/manual/CHAPTER_CellLib.tex +++ b/manual/CHAPTER_CellLib.tex @@ -437,7 +437,7 @@ otherwise. \begin{lstlisting}[mathescape,language=Verilog] always @($ClkEdge$ C, $RstEdge$ R) if (R == $RstLvl$) - Q <= $RstVa$l; + Q <= $RstVal$; else Q <= D; \end{lstlisting} |