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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-20 10:00:09 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-20 10:00:09 -0700 |
| commit | ed187ef1cf118727a8964e26c36530560f3e37db (patch) | |
| tree | 64d716705836512b1115b74a3dff5015e25c3fe0 /manual | |
| parent | 1844498c5f4f19f77919faf056b165d8b282470e (diff) | |
| download | yosys-ed187ef1cf118727a8964e26c36530560f3e37db.tar.gz yosys-ed187ef1cf118727a8964e26c36530560f3e37db.tar.bz2 yosys-ed187ef1cf118727a8964e26c36530560f3e37db.zip | |
Add a xilinx_dsp_cascade matcher for PCIN -> PCOUT
Diffstat (limited to 'manual')
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