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| author | Miodrag Milanovic <mmicko@gmail.com> | 2022-06-10 15:00:07 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2022-06-10 15:00:07 +0200 |
| commit | d1cd24a457fe7d935558975bc1d401e42bbd177e (patch) | |
| tree | e5551155f9f1a48605afe1336811454f6ddecc15 /manual | |
| parent | 1940bf647ff988587c4b3f3ef7aac056ae726f84 (diff) | |
| download | yosys-d1cd24a457fe7d935558975bc1d401e42bbd177e.tar.gz yosys-d1cd24a457fe7d935558975bc1d401e42bbd177e.tar.bz2 yosys-d1cd24a457fe7d935558975bc1d401e42bbd177e.zip | |
Update manual
Diffstat (limited to 'manual')
| -rw-r--r-- | manual/command-reference-manual.tex | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/manual/command-reference-manual.tex b/manual/command-reference-manual.tex index 4108527d8..edc8af6e6 100644 --- a/manual/command-reference-manual.tex +++ b/manual/command-reference-manual.tex @@ -7838,6 +7838,11 @@ Add Verilog library directories. Verific will search in this directories to find undefined modules. + verific -vlog-libext <extension>.. + +Add Verilog library extensions, used when searching in library directories. + + verific -vlog-define <macro>[=<value>].. Add Verilog defines. @@ -8057,6 +8062,9 @@ Options: Do not change the width of memory address ports. Use this options in flows that use the 'memory_memx' pass. + -mux_undef + remove 'undef' inputs from $mux, $pmux and $_MUX_ cells + -keepdc Do not optimize explicit don't-care values. \end{lstlisting} |