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| author | Clifford Wolf <clifford@clifford.at> | 2019-07-03 10:45:29 +0200 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2019-07-09 18:46:58 +0100 |
| commit | d105e2f03f259e4f2be3d6d9ba970565d8422b87 (patch) | |
| tree | 6414ce95494663eef768f72c6b9df65165bf85af /manual | |
| parent | 4b49c0201edc37d0d3edd906e2693d6284a1b0ba (diff) | |
| download | yosys-d105e2f03f259e4f2be3d6d9ba970565d8422b87.tar.gz yosys-d105e2f03f259e4f2be3d6d9ba970565d8422b87.tar.bz2 yosys-d105e2f03f259e4f2be3d6d9ba970565d8422b87.zip | |
Merge pull request #1154 from whitequark/manual-sync-always
manual: explain the purpose of `sync always`
Diffstat (limited to 'manual')
| -rw-r--r-- | manual/CHAPTER_Overview.tex | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/manual/CHAPTER_Overview.tex b/manual/CHAPTER_Overview.tex index 1a25c477f..3009bf2c0 100644 --- a/manual/CHAPTER_Overview.tex +++ b/manual/CHAPTER_Overview.tex @@ -331,8 +331,9 @@ to update {\tt \textbackslash{}q}. An RTLIL::Process is a container for zero or more RTLIL::SyncRule objects and exactly one RTLIL::CaseRule object, which is called the {\it root case}. -An RTLIL::SyncRule object contains an (optional) synchronization condition -(signal and edge-type) and zero or more assignments (RTLIL::SigSig). +An RTLIL::SyncRule object contains an (optional) synchronization condition (signal and edge-type) and zero or +more assignments (RTLIL::SigSig). The {\tt always} synchronization condition is used to break combinatorial +loops when a latch should be inferred instead. An RTLIL::CaseRule is a container for zero or more assignments (RTLIL::SigSig) and zero or more RTLIL::SwitchRule objects. An RTLIL::SwitchRule objects is a |