diff options
| author | Clifford Wolf <clifford@clifford.at> | 2016-05-14 11:35:39 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-05-14 11:35:39 +0200 |
| commit | d05115ceda2969badb83b3b2f0cefcd447c29451 (patch) | |
| tree | 6ab86d5016958c41fce6e6c1fcac0ba8e315fb24 /manual | |
| parent | 407cdea0bc3a3d2a258b30a3e19d0861c3c4ba6f (diff) | |
| download | yosys-d05115ceda2969badb83b3b2f0cefcd447c29451.tar.gz yosys-d05115ceda2969badb83b3b2f0cefcd447c29451.tar.bz2 yosys-d05115ceda2969badb83b3b2f0cefcd447c29451.zip | |
Minor presentation fixes
Diffstat (limited to 'manual')
| -rw-r--r-- | manual/PRESENTATION_Prog.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/manual/PRESENTATION_Prog.tex b/manual/PRESENTATION_Prog.tex index 73c2bf419..b85eda892 100644 --- a/manual/PRESENTATION_Prog.tex +++ b/manual/PRESENTATION_Prog.tex @@ -534,7 +534,7 @@ struct MyPass : public Pass { log("Modules in current design:\n"); for (auto mod : design->modules()) log(" %s (%d wires, %d cells)\n", log_id(mod), - GetSize(mod->wires), GetSize(mod->cells)); + GetSize(mod->wires()), GetSize(mod->cells())); } } MyPass; \end{lstlisting} |