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| author | whitequark <whitequark@whitequark.org> | 2019-07-02 17:10:13 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2019-07-02 17:10:13 +0000 |
| commit | 9251c000e86c1d7e757c89720f729ac984aaf901 (patch) | |
| tree | 1db94ccf88a28e50a7e01b6997cfadee9ef37163 /manual | |
| parent | 0447794c51ce1b77c2bd846ad5c09637f42f8612 (diff) | |
| download | yosys-9251c000e86c1d7e757c89720f729ac984aaf901.tar.gz yosys-9251c000e86c1d7e757c89720f729ac984aaf901.tar.bz2 yosys-9251c000e86c1d7e757c89720f729ac984aaf901.zip | |
manual: explain the purpose of `sync always`.
Diffstat (limited to 'manual')
| -rw-r--r-- | manual/CHAPTER_Overview.tex | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/manual/CHAPTER_Overview.tex b/manual/CHAPTER_Overview.tex index 1a25c477f..3009bf2c0 100644 --- a/manual/CHAPTER_Overview.tex +++ b/manual/CHAPTER_Overview.tex @@ -331,8 +331,9 @@ to update {\tt \textbackslash{}q}. An RTLIL::Process is a container for zero or more RTLIL::SyncRule objects and exactly one RTLIL::CaseRule object, which is called the {\it root case}. -An RTLIL::SyncRule object contains an (optional) synchronization condition -(signal and edge-type) and zero or more assignments (RTLIL::SigSig). +An RTLIL::SyncRule object contains an (optional) synchronization condition (signal and edge-type) and zero or +more assignments (RTLIL::SigSig). The {\tt always} synchronization condition is used to break combinatorial +loops when a latch should be inferred instead. An RTLIL::CaseRule is a container for zero or more assignments (RTLIL::SigSig) and zero or more RTLIL::SwitchRule objects. An RTLIL::SwitchRule objects is a |