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| author | Clifford Wolf <clifford@clifford.at> | 2014-09-04 02:07:52 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-09-04 02:07:52 +0200 |
| commit | 8927aa6148f5575b2da9bfb76afb4af076fe18f3 (patch) | |
| tree | 4da0980333589d4785880e48383c6f44e4a94887 /manual | |
| parent | b9cb483f3e2a498ee75a422e09164a920918362b (diff) | |
| download | yosys-8927aa6148f5575b2da9bfb76afb4af076fe18f3.tar.gz yosys-8927aa6148f5575b2da9bfb76afb4af076fe18f3.tar.bz2 yosys-8927aa6148f5575b2da9bfb76afb4af076fe18f3.zip | |
Removed $bu0 cell type
Diffstat (limited to 'manual')
| -rw-r--r-- | manual/CHAPTER_CellLib.tex | 6 | ||||
| -rw-r--r-- | manual/PRESENTATION_Prog.tex | 2 | ||||
| -rw-r--r-- | manual/command-reference-manual.tex | 2 |
3 files changed, 2 insertions, 8 deletions
diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex index 82473f6a2..5045960cb 100644 --- a/manual/CHAPTER_CellLib.tex +++ b/manual/CHAPTER_CellLib.tex @@ -97,12 +97,6 @@ The width of the output port \B{Y}. Table~\ref{tab:CellLib_binary} lists all cells for binary RTL operators. -The additional cell type {\tt \$bu0} is similar to {\tt \$pos}, but always -extends unsigned arguments with zeros. ({\tt \$pos} extends unsigned arguments -with {\tt x}-bits if the most significant bit is {\tt x}.) This is used -internally to correctly implement the {\tt ==} and {\tt !=} operators for -constant arguments. - \subsection{Multiplexers} Multiplexers are generated by the Verilog HDL frontend for {\tt diff --git a/manual/PRESENTATION_Prog.tex b/manual/PRESENTATION_Prog.tex index 4e9f4b21e..590451be0 100644 --- a/manual/PRESENTATION_Prog.tex +++ b/manual/PRESENTATION_Prog.tex @@ -300,7 +300,7 @@ The {\tt type} may refer to another module in the same design, a cell name from cell name from the internal cell library: \begin{lstlisting}[xleftmargin=1cm, basicstyle=\ttfamily\fontsize{6pt}{7pt}\selectfont] -$not $pos $bu0 $neg $and $or $xor $xnor $reduce_and $reduce_or $reduce_xor $reduce_xnor +$not $pos $neg $and $or $xor $xnor $reduce_and $reduce_or $reduce_xor $reduce_xnor $reduce_bool $shl $shr $sshl $sshr $lt $le $eq $ne $eqx $nex $ge $gt $add $sub $mul $div $mod $pow $logic_not $logic_and $logic_or $mux $pmux $slice $concat $lut $assert $sr $dff $dffsr $adff $dlatch $dlatchsr $memrd $memwr $mem $fsm $_NOT_ $_AND_ $_OR_ $_XOR_ $_MUX_ $_SR_NN_ diff --git a/manual/command-reference-manual.tex b/manual/command-reference-manual.tex index 54fec542a..9d9665c1e 100644 --- a/manual/command-reference-manual.tex +++ b/manual/command-reference-manual.tex @@ -1204,7 +1204,7 @@ unless another prefix is specified using -prefix <prefix>. This pass maps a small selection of simple coarse-grain cells to yosys gate primitives. The following internal cell types are mapped by this pass: - $not, $pos, $bu0, $and, $or, $xor, $xnor + $not, $pos, $and, $or, $xor, $xnor $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor, $reduce_bool $logic_not, $logic_and, $logic_or, $mux $sr, $dff, $dffsr, $adff, $dlatch |