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| author | Clifford Wolf <clifford@clifford.at> | 2016-08-11 11:17:44 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2016-08-11 11:17:44 +0200 |
| commit | 6ac67eac10cfd3e9508ef02f6301455fc3c13451 (patch) | |
| tree | 0bc8e5443364fd771c117b29a2b9b0d62a6a939e /manual | |
| parent | e9fe57c75e225f80156ceabbc10741c3cfee1c87 (diff) | |
| parent | 0515809448d11beae27a6199ea02c59b36b58299 (diff) | |
| download | yosys-6ac67eac10cfd3e9508ef02f6301455fc3c13451.tar.gz yosys-6ac67eac10cfd3e9508ef02f6301455fc3c13451.tar.bz2 yosys-6ac67eac10cfd3e9508ef02f6301455fc3c13451.zip | |
Merge pull request #198 from whitequark/master
synth_greenpak4: use attrmvcp to move LOC from wires to cells
Diffstat (limited to 'manual')
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