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| author | Miodrag Milanovic <mmicko@gmail.com> | 2021-11-05 10:04:15 +0100 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2021-11-05 10:04:15 +0100 |
| commit | 598f51c6a1e4542e40eaf82490e171d23d0265fc (patch) | |
| tree | 0676994e64c6840d836bf5d47639da13d40395b6 /manual | |
| parent | 5a5244a12eaeb56b07437223ee79e28e1cf8003c (diff) | |
| download | yosys-598f51c6a1e4542e40eaf82490e171d23d0265fc.tar.gz yosys-598f51c6a1e4542e40eaf82490e171d23d0265fc.tar.bz2 yosys-598f51c6a1e4542e40eaf82490e171d23d0265fc.zip | |
Update command reference
Diffstat (limited to 'manual')
| -rw-r--r-- | manual/command-reference-manual.tex | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/manual/command-reference-manual.tex b/manual/command-reference-manual.tex index b3ab02b97..ccfae8bff 100644 --- a/manual/command-reference-manual.tex +++ b/manual/command-reference-manual.tex @@ -3654,6 +3654,11 @@ Additional -D<macro>[=<value>] options may be added after the option indicating the language version (and before file names) to set additional verilog defines. + read {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} <vhdl-file>.. + +Load the specified VHDL files. (Requires Verific.) + + read {-f|-F} <command-file> Load and execute the specified command file. (Requires Verific.) @@ -7316,6 +7321,11 @@ The macros SYNTHESIS and VERIFIC are defined implicitly. Like -sv, but define FORMAL instead of SYNTHESIS. + verific {-vhdl87|-vhdl93|-vhdl2k|-vhdl2008|-vhdl} <vhdl-file>.. + +Load the specified VHDL files into Verific. + + verific {-f|-F} <command-file> Load and execute the specified command file. @@ -7502,6 +7512,13 @@ Templates: WARNING: Templates only available in commercial build. + + + verific -cfg [<name> [<value>]] + +Get/set Verific runtime flags. + + Use YosysHQ Tabby CAD Suite if you need Yosys+Verific. https://www.yosyshq.com/ |