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| author | Clifford Wolf <clifford@clifford.at> | 2016-07-30 12:50:39 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2016-07-30 12:50:39 +0200 |
| commit | 21e1bac0846e01fb58ae1fd42215b92f245ae18d (patch) | |
| tree | 43c1c9fff3a78d7221c6e5dfbfebe820b311afa1 /manual | |
| parent | 5fe13a16eaaee4ac53523b5325cb9d92b5a1150d (diff) | |
| parent | da56a5bbc60e58c305227105b68654264738c241 (diff) | |
| download | yosys-21e1bac0846e01fb58ae1fd42215b92f245ae18d.tar.gz yosys-21e1bac0846e01fb58ae1fd42215b92f245ae18d.tar.bz2 yosys-21e1bac0846e01fb58ae1fd42215b92f245ae18d.zip | |
Merge branch 'master' of github.com:cliffordwolf/yosys
Diffstat (limited to 'manual')
| -rw-r--r-- | manual/CHAPTER_CellLib.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex index 0f1136346..bff01d06c 100644 --- a/manual/CHAPTER_CellLib.tex +++ b/manual/CHAPTER_CellLib.tex @@ -421,7 +421,7 @@ pass. The combinatorial logic cells can be mapped to physical cells from a Liber using the {\tt abc} pass. \begin{fixme} -Add information about {\tt \$assert}, {\tt \$assume}, {\tt \$predict}, {\tt \$equiv}, and {\tt \$initstate} cells. +Add information about {\tt \$assert}, {\tt \$assume}, {\tt \$predict}, {\tt \$equiv}, {\tt \$initstate}, {\tt \$aconst}, and {\tt \$anyconst} cells. \end{fixme} \begin{fixme} |