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author | Clifford Wolf <clifford@clifford.at> | 2014-07-31 02:32:00 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-07-31 02:32:00 +0200 |
commit | 1202f7aa4bb0f9afde157ebc4701d64e7e38abd8 (patch) | |
tree | d1a4bb9dfe62ac911ca4751a98b3b63dba22af40 /manual | |
parent | 6ca0c569d92883b6eac1725204de90aee4af31bc (diff) | |
download | yosys-1202f7aa4bb0f9afde157ebc4701d64e7e38abd8.tar.gz yosys-1202f7aa4bb0f9afde157ebc4701d64e7e38abd8.tar.bz2 yosys-1202f7aa4bb0f9afde157ebc4701d64e7e38abd8.zip |
Renamed "stdcells.v" to "techmap.v"
Diffstat (limited to 'manual')
-rw-r--r-- | manual/CHAPTER_Techmap.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/manual/CHAPTER_Techmap.tex b/manual/CHAPTER_Techmap.tex index be74c3567..26632d0b5 100644 --- a/manual/CHAPTER_Techmap.tex +++ b/manual/CHAPTER_Techmap.tex @@ -27,7 +27,7 @@ cells with the provided implementation. When no map file is provided, {\tt techmap} uses a built-in map file that maps the Yosys RTL cell types to the internal gate library used by Yosys. -The curious reader may find this map file as {\tt techlibs/common/stdcells.v} in +The curious reader may find this map file as {\tt techlibs/common/techmap.v} in the Yosys source tree. Additional features have been added to {\tt techmap} to allow for conditional |