Merge branch 'master' of https://github.com/cliffordwolf/yosys into btor

added case for memwr cell that is used in muxes (same cell is used more than one time)
corrected bug for xnor and logic_not
added pmux cell translation

Conflicts:
	backends/btor/btor.cc

1 files changed, 3 insertions, 3 deletions

diff --git a/manual/manual.tex b/manual/manual.tex
index d6ffd95a6..19d3b7b2f 100644
--- a/manual/manual.tex
+++ b/manual/manual.tex
@@ -140,11 +140,11 @@ bookmarksopen=false%
 \eject
 
 \chapter*{Abstract}
-Most of todays digital design is done in HDL code (mostly Verilog or VHDL) and
+Most of today's digital design is done in HDL code (mostly Verilog or VHDL) and
 with the help of HDL synthesis tools.
 
 In special cases such as synthesis for coarse-grain cell libraries or when
-testing new synthesis algorithms it might be neccessary to write a custom HDL
+testing new synthesis algorithms it might be necessary to write a custom HDL
 synthesis tool or add new features to an existing one. It this cases the
 availability of a Free and Open Source (FOSS) synthesis tool that can be used
 as basis for custom tools would be helpful.
@@ -158,7 +158,7 @@ by Yosys to perform advanced gate-level optimizations.
 An evaluation of Yosys based on real-world designs is included. It is shown
 that Yosys can be used as-is to synthesize such designs. The results produced
 by Yosys in this tests where successflly verified using formal verification
-and are compareable in quality to the results produced by a commercial
+and are comparable in quality to the results produced by a commercial
 synthesis tool.
 
 \bigskip