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| author | Clifford Wolf <clifford@clifford.at> | 2018-08-15 14:05:38 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-08-15 14:05:38 +0200 |
| commit | 67b10262975340e0b53f8d1072ac2e1c1f087fb1 (patch) | |
| tree | c10a6e56f6f5b61ce3fbff7c165207cc40d704c8 /manual/PRESENTATION_Prog/my_cmd.cc | |
| parent | d8e40c75eb96e7f3c995b2acd018b5cba6005cdd (diff) | |
| parent | 3aa4484a3cd9a2e82fddd499cde575eaf8c565cc (diff) | |
| download | yosys-67b10262975340e0b53f8d1072ac2e1c1f087fb1.tar.gz yosys-67b10262975340e0b53f8d1072ac2e1c1f087fb1.tar.bz2 yosys-67b10262975340e0b53f8d1072ac2e1c1f087fb1.zip | |
Merge pull request #591 from hzeller/virtual-override
Consistent use of 'override' for virtual methods in derived classes.
Diffstat (limited to 'manual/PRESENTATION_Prog/my_cmd.cc')
| -rw-r--r-- | manual/PRESENTATION_Prog/my_cmd.cc | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/manual/PRESENTATION_Prog/my_cmd.cc b/manual/PRESENTATION_Prog/my_cmd.cc index d99bfe1e8..5d9a7e13b 100644 --- a/manual/PRESENTATION_Prog/my_cmd.cc +++ b/manual/PRESENTATION_Prog/my_cmd.cc @@ -6,7 +6,7 @@ PRIVATE_NAMESPACE_BEGIN struct MyPass : public Pass { MyPass() : Pass("my_cmd", "just a simple test") { } - virtual void execute(std::vector<std::string> args, RTLIL::Design *design) + void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE { log("Arguments to my_cmd:\n"); for (auto &arg : args) @@ -22,7 +22,7 @@ struct MyPass : public Pass { struct Test1Pass : public Pass { Test1Pass() : Pass("test1", "creating the absval module") { } - virtual void execute(std::vector<std::string>, RTLIL::Design *design) + void execute(std::vector<std::string>, RTLIL::Design *design) YS_OVERRIDE { if (design->has("\\absval") != 0) log_error("A module with the name absval already exists!\n"); @@ -49,7 +49,7 @@ struct Test1Pass : public Pass { struct Test2Pass : public Pass { Test2Pass() : Pass("test2", "demonstrating sigmap on test module") { } - virtual void execute(std::vector<std::string>, RTLIL::Design *design) + void execute(std::vector<std::string>, RTLIL::Design *design) YS_OVERRIDE { if (design->selection_stack.back().empty()) log_cmd_error("This command can't operator on an empty selection!\n"); |