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| author | Clifford Wolf <clifford@clifford.at> | 2014-06-21 16:33:33 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-06-21 16:33:33 +0200 |
| commit | b18fa95d2f1f4118cdb7c16e3415059bd81e2325 (patch) | |
| tree | 68ba5ef340312a0d5f3a63108dddf034e8e6dba6 /manual/PRESENTATION_ExOth/equiv.ys | |
| parent | 1c85584fe5843a43590de3927fe9bde74a04e72e (diff) | |
| download | yosys-b18fa95d2f1f4118cdb7c16e3415059bd81e2325.tar.gz yosys-b18fa95d2f1f4118cdb7c16e3415059bd81e2325.tar.bz2 yosys-b18fa95d2f1f4118cdb7c16e3415059bd81e2325.zip | |
Progress in presentation
Diffstat (limited to 'manual/PRESENTATION_ExOth/equiv.ys')
| -rw-r--r-- | manual/PRESENTATION_ExOth/equiv.ys | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/manual/PRESENTATION_ExOth/equiv.ys b/manual/PRESENTATION_ExOth/equiv.ys new file mode 100644 index 000000000..09a4045db --- /dev/null +++ b/manual/PRESENTATION_ExOth/equiv.ys @@ -0,0 +1,17 @@ +# read test design +read_verilog ../PRESENTATION_ExSyn/techmap_01.v +hierarchy -top test + +# create two version of the design: test_orig and test_mapped +copy test test_orig +rename test test_mapped + +# apply the techmap only to test_mapped +techmap -map ../PRESENTATION_ExSyn/techmap_01_map.v test_mapped + +# create a miter circuit to test equivialence +miter -equiv -make_assert -make_outputs test_orig test_mapped miter +flatten miter + +# run equivialence check +sat -verify -prove-asserts -show-inputs -show-outputs miter |