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author | Clifford Wolf <clifford@clifford.at> | 2014-02-21 14:59:59 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-02-21 14:59:59 +0100 |
commit | 79edcd4318590974ef49b2d5f561382eea3454bf (patch) | |
tree | 0b6a309ed5aa66508f53b450e9d488ae0f65d59e /manual/PRESENTATION_ExAdv/macc_xilinx_wrap_map.v | |
parent | 038eac741415c3d7ddef3a1e9348586e7ba3d4ad (diff) | |
download | yosys-79edcd4318590974ef49b2d5f561382eea3454bf.tar.gz yosys-79edcd4318590974ef49b2d5f561382eea3454bf.tar.bz2 yosys-79edcd4318590974ef49b2d5f561382eea3454bf.zip |
Progress in presentation
Diffstat (limited to 'manual/PRESENTATION_ExAdv/macc_xilinx_wrap_map.v')
-rw-r--r-- | manual/PRESENTATION_ExAdv/macc_xilinx_wrap_map.v | 12 |
1 files changed, 5 insertions, 7 deletions
diff --git a/manual/PRESENTATION_ExAdv/macc_xilinx_wrap_map.v b/manual/PRESENTATION_ExAdv/macc_xilinx_wrap_map.v index d1ded2954..f23f6c02a 100644 --- a/manual/PRESENTATION_ExAdv/macc_xilinx_wrap_map.v +++ b/manual/PRESENTATION_ExAdv/macc_xilinx_wrap_map.v @@ -1,4 +1,3 @@ - (* techmap_celltype = "$mul" *) module mul_wrap (A, B, Y); @@ -12,8 +11,8 @@ input [A_WIDTH-1:0] A; input [B_WIDTH-1:0] B; output [Y_WIDTH-1:0] Y; -wire [24:0] A_25 = A; -wire [17:0] B_18 = B; +wire [17:0] A_18 = A; +wire [24:0] B_25 = B; wire [47:0] Y_48; assign Y = Y_48; @@ -26,7 +25,7 @@ initial begin _TECHMAP_FAIL_ <= 1; if (A_WIDTH < 4 || B_WIDTH < 4) _TECHMAP_FAIL_ <= 1; - if (A_WIDTH > 25 || B_WIDTH > 18) + if (A_WIDTH > 18 || B_WIDTH > 25) _TECHMAP_FAIL_ <= 1; if (A_WIDTH*B_WIDTH < 100) _TECHMAP_FAIL_ <= 1; @@ -39,8 +38,8 @@ end .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH) ) _TECHMAP_REPLACE_ ( - .A(A_25), - .B(B_18), + .A(A_18), + .B(B_25), .Y(Y_48) ); @@ -88,4 +87,3 @@ end ); endmodule - |