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| author | Clifford Wolf <clifford@clifford.at> | 2013-11-21 13:49:00 +0100 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2013-11-21 13:49:00 +0100 |
| commit | 09471846c553855c43224ce32d855c46f4df5140 (patch) | |
| tree | 659fff2b882e2d7c54a5eaf72adeed2328d4ba64 /manual/CHAPTER_Verilog.tex | |
| parent | 84ced2bb8ee2e6498b53ae6cdb77930aa98affbb (diff) | |
| download | yosys-09471846c553855c43224ce32d855c46f4df5140.tar.gz yosys-09471846c553855c43224ce32d855c46f4df5140.tar.bz2 yosys-09471846c553855c43224ce32d855c46f4df5140.zip | |
Major improvements in mem2reg and added "init" sync rules
Diffstat (limited to 'manual/CHAPTER_Verilog.tex')
0 files changed, 0 insertions, 0 deletions