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authorClifford Wolf <clifford@clifford.at>2014-01-28 06:55:47 +0100
committerClifford Wolf <clifford@clifford.at>2014-01-28 06:55:47 +0100
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+module uut_always01(clock,
+ reset, count);
+
+input clock, reset;
+output [3:0] count;
+reg [3:0] count;
+
+always @(posedge clock)
+ count <= reset ?
+ 0 : count + 1;
+
+
+
+endmodule