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| author | Clifford Wolf <clifford@clifford.at> | 2015-07-02 11:14:30 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2015-07-02 11:14:30 +0200 |
| commit | 6c84341f22b2758181164e8d5cddd23e3589c90b (patch) | |
| tree | 0438ad9becf956e43ebf8665fee89e021b13bcdf /manual/CHAPTER_Intro.tex | |
| parent | 053058d78167f7f1ec377fddcee8b648a5ae4138 (diff) | |
| download | yosys-6c84341f22b2758181164e8d5cddd23e3589c90b.tar.gz yosys-6c84341f22b2758181164e8d5cddd23e3589c90b.tar.bz2 yosys-6c84341f22b2758181164e8d5cddd23e3589c90b.zip | |
Fixed trailing whitespaces
Diffstat (limited to 'manual/CHAPTER_Intro.tex')
| -rw-r--r-- | manual/CHAPTER_Intro.tex | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/manual/CHAPTER_Intro.tex b/manual/CHAPTER_Intro.tex index f735d46b2..76e5d847b 100644 --- a/manual/CHAPTER_Intro.tex +++ b/manual/CHAPTER_Intro.tex @@ -35,7 +35,7 @@ The proposed custom HDL synthesis tool should be licensed under a Free and Open Source Software (FOSS) licence. So an existing FOSS Verilog or VHDL synthesis tool would have been needed as basis to build upon. The main advantages of choosing Verilog or VHDL is the ability to synthesize existing HDL code and -to mitigate the requirement for circuit-designers to learn a new language. In order to take full advantage of any existing FOSS Verilog or VHDL tool, +to mitigate the requirement for circuit-designers to learn a new language. In order to take full advantage of any existing FOSS Verilog or VHDL tool, such a tool would have to provide a feature-complete implementation of the synthesizable HDL subset. @@ -68,7 +68,7 @@ problem of implementing a HDL synthesis tool is approached in the case of Yosys. Chapter~\ref{chapter:overview} contains a more detailed overview of the -implementation of Yosys. This chapter covers the data structures used in +implementation of Yosys. This chapter covers the data structures used in Yosys to represent a design in detail and is therefore recommended reading for everyone who is interested in understanding the Yosys internals. @@ -81,7 +81,7 @@ is recommended reading for everyone who actually wants to read or write Yosys source code. The chapter concludes with an example loadable module for Yosys. -Chapters~\ref{chapter:verilog}, \ref{chapter:opt}, and \ref{chapter:techmap} +Chapters~\ref{chapter:verilog}, \ref{chapter:opt}, and \ref{chapter:techmap} cover three important pieces of the synthesis pipeline: The Verilog frontend, the optimization passes and the technology mapping to the target architecture, respectively. |