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| author | whitequark <whitequark@whitequark.org> | 2018-12-20 07:59:40 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2018-12-20 07:59:40 +0000 |
| commit | c04908c99740e616cae454aa6a5d7a3dd13af2fa (patch) | |
| tree | a38cad87f651164ab9c7c746ecb963a17b3a9f71 /manual/CHAPTER_CellLib.tex | |
| parent | a9ff81dd82d347b5ed867f142e61271aa40d85ee (diff) | |
| download | yosys-c04908c99740e616cae454aa6a5d7a3dd13af2fa.tar.gz yosys-c04908c99740e616cae454aa6a5d7a3dd13af2fa.tar.bz2 yosys-c04908c99740e616cae454aa6a5d7a3dd13af2fa.zip | |
manual: fix typos.
Diffstat (limited to 'manual/CHAPTER_CellLib.tex')
| -rw-r--r-- | manual/CHAPTER_CellLib.tex | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex index 6589bb2e7..65a79020f 100644 --- a/manual/CHAPTER_CellLib.tex +++ b/manual/CHAPTER_CellLib.tex @@ -254,7 +254,7 @@ enable bit for each data bit), an address input \B{ADDR} and a data input \begin{itemize} \item \B{MEMID} \\ -The name of the RTLIL::Memory object that is associated with this read port. +The name of the RTLIL::Memory object that is associated with this write port. \item \B{ABITS} \\ The number of address bits (width of the \B{ADDR} input port). @@ -263,7 +263,7 @@ The number of address bits (width of the \B{ADDR} input port). The number of data bits (width of the \B{DATA} output port). \item \B{CLK\_ENABLE} \\ -When this parameter is non-zero, the clock is used. Otherwise this read port is asynchronous and +When this parameter is non-zero, the clock is used. Otherwise this write port is asynchronous and the \B{CLK} input is not used. \item \B{CLK\_POLARITY} \\ |