Merge branch 'master' of https://github.com/cliffordwolf/yosys

1 files changed, 10 insertions, 2 deletions

diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex
index 64d3633e9..c9bf978a9 100644
--- a/manual/CHAPTER_CellLib.tex
+++ b/manual/CHAPTER_CellLib.tex
@@ -357,7 +357,7 @@ Add a brief description of the {\tt \$fsm} cell type.
 For gate level logic networks, fixed function single bit cells are used that do
 not provide any parameters.
 
-Simulation models for these cells can be found in the file {\tt techlibs/common/stdcells\_sim.v} in the Yosys
+Simulation models for these cells can be found in the file {\tt techlibs/common/simcells.v} in the Yosys
 source tree.
 
 \begin{table}[t]
@@ -417,7 +417,7 @@ pass. The combinatorial logic cells can be mapped to physical cells from a Liber
 using the {\tt abc} pass.
 
 \begin{fixme}
-Add information about {\tt \$assert} cells.
+Add information about {\tt \$assert}, {\tt \$assume}, and {\tt \$equiv} cells.
 \end{fixme}
 
 \begin{fixme}
@@ -429,6 +429,14 @@ Add information about {\tt \$alu}, {\tt \$macc}, {\tt \$fa}, and {\tt \$lcu} cel
 \end{fixme}
 
 \begin{fixme}
+Add information about {\tt \$dffe}, {\tt \$dffsr}, {\tt \$dlatch}, and {\tt \$dlatchsr} cells.
+\end{fixme}
+
+\begin{fixme}
+Add information about {\tt \$\_DFFE\_??\_}, {\tt \$\_DFFSR\_???\_}, {\tt \$\_DLATCH\_?\_}, and {\tt \$\_DLATCHSR\_???\_} cells.
+\end{fixme}
+
+\begin{fixme}
 Add information about {\tt \$\_NAND\_}, {\tt \$\_NOR\_}, {\tt \$\_XNOR\_}, {\tt \$\_AOI3\_}, {\tt \$\_OAI3\_}, {\tt \$\_AOI4\_}, and {\tt \$\_OAI4\_} cells.
 \end{fixme}