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| author | Clifford Wolf <clifford@clifford.at> | 2016-08-30 19:09:56 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2016-08-30 19:09:56 +0200 |
| commit | 6f41e5277d1d41db7a620c73cf1b65558b55f236 (patch) | |
| tree | 45cad8b0cafc31392a3fe71a505b442ee6a61ed7 /manual/CHAPTER_CellLib.tex | |
| parent | a8124c137e2bfa3605dacadfe469ea22934b4cb3 (diff) | |
| download | yosys-6f41e5277d1d41db7a620c73cf1b65558b55f236.tar.gz yosys-6f41e5277d1d41db7a620c73cf1b65558b55f236.tar.bz2 yosys-6f41e5277d1d41db7a620c73cf1b65558b55f236.zip | |
Removed $aconst cell type
Diffstat (limited to 'manual/CHAPTER_CellLib.tex')
| -rw-r--r-- | manual/CHAPTER_CellLib.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex index a839e0c43..bd73ae23c 100644 --- a/manual/CHAPTER_CellLib.tex +++ b/manual/CHAPTER_CellLib.tex @@ -421,7 +421,7 @@ pass. The combinatorial logic cells can be mapped to physical cells from a Liber using the {\tt abc} pass. \begin{fixme} -Add information about {\tt \$assert}, {\tt \$assume}, {\tt \$equiv}, {\tt \$initstate}, {\tt \$aconst}, and {\tt \$anyconst} cells. +Add information about {\tt \$assert}, {\tt \$assume}, {\tt \$equiv}, {\tt \$initstate}, and {\tt \$anyconst} cells. \end{fixme} \begin{fixme} |