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| author | Clifford Wolf <clifford@clifford.at> | 2017-02-04 14:14:26 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-02-04 14:14:26 +0100 |
| commit | 3928482a3c4fb71b8e6ccdcb362c030eef34a479 (patch) | |
| tree | 482ea8a72c3bae5bafc377136d10426898cb8ac5 /manual/CHAPTER_CellLib.tex | |
| parent | 911c44d164e04026bd3a3a2eb1bf0c5d9cca5c19 (diff) | |
| download | yosys-3928482a3c4fb71b8e6ccdcb362c030eef34a479.tar.gz yosys-3928482a3c4fb71b8e6ccdcb362c030eef34a479.tar.bz2 yosys-3928482a3c4fb71b8e6ccdcb362c030eef34a479.zip | |
Add $cover cell type and SVA cover() support
Diffstat (limited to 'manual/CHAPTER_CellLib.tex')
| -rw-r--r-- | manual/CHAPTER_CellLib.tex | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex index a831fdf33..7686f5963 100644 --- a/manual/CHAPTER_CellLib.tex +++ b/manual/CHAPTER_CellLib.tex @@ -421,7 +421,7 @@ pass. The combinatorial logic cells can be mapped to physical cells from a Liber using the {\tt abc} pass. \begin{fixme} -Add information about {\tt \$assert}, {\tt \$assume}, {\tt \$equiv}, {\tt \$initstate}, {\tt \$anyconst}, and {\tt \$anyseq} cells. +Add information about {\tt \$assert}, {\tt \$assume}, {\tt \$cover}, {\tt \$equiv}, {\tt \$initstate}, {\tt \$anyconst}, and {\tt \$anyseq} cells. \end{fixme} \begin{fixme} |