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| author | Clifford Wolf <clifford@clifford.at> | 2013-09-15 11:52:57 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-09-15 11:52:57 +0200 |
| commit | 288ba9618af9c5ba9db1131955c92d59166d120d (patch) | |
| tree | d65852d388355322a9e7166ba0b0661e24eb220e /manual/CHAPTER_CellLib.tex | |
| parent | 647c23b7b7e3a72fc64d9b1ad07dacd590865898 (diff) | |
| download | yosys-288ba9618af9c5ba9db1131955c92d59166d120d.tar.gz yosys-288ba9618af9c5ba9db1131955c92d59166d120d.tar.bz2 yosys-288ba9618af9c5ba9db1131955c92d59166d120d.zip | |
Moved common techlib files to techlibs/common
Diffstat (limited to 'manual/CHAPTER_CellLib.tex')
| -rw-r--r-- | manual/CHAPTER_CellLib.tex | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex index b4f988129..09be0870e 100644 --- a/manual/CHAPTER_CellLib.tex +++ b/manual/CHAPTER_CellLib.tex @@ -22,7 +22,7 @@ Note that all RTL cells have parameters indicating the size of inputs and output passes modify RTL cells they must always keep the values of these parameters in sync with the size of the signals connected to the inputs and outputs. -Simulation models for the RTL cells can be found in the file {\tt techlibs/simlib.v} in the Yosys +Simulation models for the RTL cells can be found in the file {\tt techlibs/common/simlib.v} in the Yosys source tree. \subsection{Unary Operators} @@ -347,7 +347,7 @@ Add a brief description of the {\tt \$fsm} cell type. For gate level logic networks, fixed function single bit cells are used that do not provide any parameters. -Simulation models for these cells can be found in the file {\tt techlibs/stdcells\_sim.v} in the Yosys +Simulation models for these cells can be found in the file {\tt techlibs/common/stdcells\_sim.v} in the Yosys source tree. \begin{table}[t] |