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author | Clifford Wolf <clifford@clifford.at> | 2013-11-29 12:51:16 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2013-11-29 12:51:16 +0100 |
commit | e23a0072ec75ce19733fb4ae04e623b17dbbd475 (patch) | |
tree | 4fc20e79abc9fbfb7a03978d94807ab778c5f1b6 /manual/APPNOTE_011_Design_Investigation/example.v | |
parent | 1b3a60976d0f74791277515cfad20dc7e37e1b9a (diff) | |
download | yosys-e23a0072ec75ce19733fb4ae04e623b17dbbd475.tar.gz yosys-e23a0072ec75ce19733fb4ae04e623b17dbbd475.tar.bz2 yosys-e23a0072ec75ce19733fb4ae04e623b17dbbd475.zip |
Progress on AppNote 011
Diffstat (limited to 'manual/APPNOTE_011_Design_Investigation/example.v')
-rw-r--r-- | manual/APPNOTE_011_Design_Investigation/example.v | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/manual/APPNOTE_011_Design_Investigation/example.v b/manual/APPNOTE_011_Design_Investigation/example.v index ec272011c..8c71989b3 100644 --- a/manual/APPNOTE_011_Design_Investigation/example.v +++ b/manual/APPNOTE_011_Design_Investigation/example.v @@ -1,5 +1,6 @@ -module example(input clk, a, b, c, output reg [1:0] y); -always @(posedge clk) - if (c) - y <= c ? a + b : 2'd0; +module example(input clk, a, b, c, + output reg [1:0] y); + always @(posedge clk) + if (c) + y <= c ? a + b : 2'd0; endmodule |