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| author | Clifford Wolf <clifford@clifford.at> | 2013-11-28 13:48:38 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-11-28 13:48:38 +0100 |
| commit | 6dfb66d26298662b4e64d55cf3c9f07738528ebc (patch) | |
| tree | 836083510396a150cb6668637757609354047f4c /manual/APPNOTE_011_Design_Investigation/example.v | |
| parent | 5af7f4db72586a8cc8c1e685eb5af8f635e91718 (diff) | |
| download | yosys-6dfb66d26298662b4e64d55cf3c9f07738528ebc.tar.gz yosys-6dfb66d26298662b4e64d55cf3c9f07738528ebc.tar.bz2 yosys-6dfb66d26298662b4e64d55cf3c9f07738528ebc.zip | |
Started writing appnote 011
Diffstat (limited to 'manual/APPNOTE_011_Design_Investigation/example.v')
| -rw-r--r-- | manual/APPNOTE_011_Design_Investigation/example.v | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/manual/APPNOTE_011_Design_Investigation/example.v b/manual/APPNOTE_011_Design_Investigation/example.v new file mode 100644 index 000000000..ec272011c --- /dev/null +++ b/manual/APPNOTE_011_Design_Investigation/example.v @@ -0,0 +1,5 @@ +module example(input clk, a, b, c, output reg [1:0] y); +always @(posedge clk) + if (c) + y <= c ? a + b : 2'd0; +endmodule |