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| author | Claire Xenia Wolf <claire@clairexen.net> | 2021-06-09 12:33:41 +0200 |
|---|---|---|
| committer | Claire Xenia Wolf <claire@clairexen.net> | 2021-06-09 12:33:41 +0200 |
| commit | a734face3a200a6704342e61466ca85fc0c732b0 (patch) | |
| tree | 6a3e2d05816d67d44c972c74e577dd3b14cde305 /manual/APPNOTE_010_Verilog_to_BLIF.tex | |
| parent | 0ada13cbe2f8e3c8568bc7e6731be9edb4c46e47 (diff) | |
| download | yosys-a734face3a200a6704342e61466ca85fc0c732b0.tar.gz yosys-a734face3a200a6704342e61466ca85fc0c732b0.tar.bz2 yosys-a734face3a200a6704342e61466ca85fc0c732b0.zip | |
More deadname stuff
Diffstat (limited to 'manual/APPNOTE_010_Verilog_to_BLIF.tex')
| -rw-r--r-- | manual/APPNOTE_010_Verilog_to_BLIF.tex | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/manual/APPNOTE_010_Verilog_to_BLIF.tex b/manual/APPNOTE_010_Verilog_to_BLIF.tex index 0d0d3e5cd..16254d593 100644 --- a/manual/APPNOTE_010_Verilog_to_BLIF.tex +++ b/manual/APPNOTE_010_Verilog_to_BLIF.tex @@ -52,7 +52,7 @@ \begin{document} \title{Yosys Application Note 010: \\ Converting Verilog to BLIF} -\author{Clifford Wolf \\ November 2013} +\author{Claire Xenia Wolf \\ November 2013} \maketitle \begin{abstract} @@ -437,12 +437,12 @@ design to fit a certain need without actually touching the RTL code. \begin{thebibliography}{9} \bibitem{yosys} -Clifford Wolf. The Yosys Open SYnthesis Suite. \\ +Claire Xenia Wolf. The Yosys Open SYnthesis Suite. \\ \url{https://yosyshq.net/yosys/} \bibitem{bigsim} yosys-bigsim, a collection of real-world Verilog designs for regression testing purposes. \\ -\url{https://github.com/cliffordwolf/yosys-bigsim} +\url{https://github.com/YosysHQ/yosys-bigsim} \bibitem{navre} Sebastien Bourdeauducq. Navr\'e AVR clone (8-bit RISC). \\ |