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| author | Icenowy Zheng <icenowy@aosc.io> | 2018-12-14 16:46:01 +0800 |
|---|---|---|
| committer | Icenowy Zheng <icenowy@aosc.io> | 2018-12-17 23:20:40 +0800 |
| commit | 634d7d1c1424c69d983c008cfd800c0d7db43379 (patch) | |
| tree | 4eab18332175e81befe8b63f4caab3f5018cf4c5 /libs | |
| parent | dc6e63d8cd138ef36ac8cbc892c2f262b7bf01c5 (diff) | |
| download | yosys-634d7d1c1424c69d983c008cfd800c0d7db43379.tar.gz yosys-634d7d1c1424c69d983c008cfd800c0d7db43379.tar.bz2 yosys-634d7d1c1424c69d983c008cfd800c0d7db43379.zip | |
Revert "Leave only real black box cells"
This reverts commit 43030db5fff285de85096aaf5578b0548659f6b7.
For a synthesis tool, generating EG_LOGIC cells are a good choice, as
they can be furtherly optimized when PnR, although sometimes EG_LOGIC is
not as blackbox as EG_PHY cells (because the latter is more close to the
hardware implementation).
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Diffstat (limited to 'libs')
0 files changed, 0 insertions, 0 deletions