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| author | Olof Kindgren <olof.kindgren@gmail.com> | 2018-05-17 13:54:40 +0200 |
|---|---|---|
| committer | Olof Kindgren <olof.kindgren@gmail.com> | 2018-05-17 13:54:43 +0200 |
| commit | faac2c559565a25e58ce95a7ea873df0c30375dc (patch) | |
| tree | a2bf6419d36745d2d30c45f7a60060ccc57b49b9 /libs/bigint | |
| parent | a7281930c5877b34e072d90d5ca013f8fda7e2cc (diff) | |
| download | yosys-faac2c559565a25e58ce95a7ea873df0c30375dc.tar.gz yosys-faac2c559565a25e58ce95a7ea873df0c30375dc.tar.bz2 yosys-faac2c559565a25e58ce95a7ea873df0c30375dc.zip | |
Avoid mixing module port declaration styles in ice40 cells_sim.v
The current code requires workarounds for several simulators
For modelsim, the file must be compiled with -mixedansiports and
xsim needs --relax.
Diffstat (limited to 'libs/bigint')
0 files changed, 0 insertions, 0 deletions