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| author | Ahmed Irfan <ahmedirfan1983@gmail.com> | 2014-01-17 10:07:05 -0800 |
|---|---|---|
| committer | Ahmed Irfan <ahmedirfan1983@gmail.com> | 2014-01-17 10:07:05 -0800 |
| commit | f2ee57f79875e8c63d5da9aedd7c33fc847e6977 (patch) | |
| tree | 7650d4822f935efd2b8b0a3f356b7f95760390ec /kernel | |
| parent | 2d7bcaf2f2ddfaa3b206421513a6fb44077f5824 (diff) | |
| parent | 6170cfe9cddfd0040fa9f7b535d25dd2c99cdb91 (diff) | |
| download | yosys-f2ee57f79875e8c63d5da9aedd7c33fc847e6977.tar.gz yosys-f2ee57f79875e8c63d5da9aedd7c33fc847e6977.tar.bz2 yosys-f2ee57f79875e8c63d5da9aedd7c33fc847e6977.zip | |
Merge pull request #4 from cliffordwolf/master
verilog defaults
Diffstat (limited to 'kernel')
| -rw-r--r-- | kernel/rtlil.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 504fdbbdc..e0b3a693d 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -227,6 +227,9 @@ struct RTLIL::Selection { if (!full_selection && selected_modules.count(module->name) == 0) selected_members[module->name].insert(member->name); } + bool empty() const { + return !full_selection && selected_modules.empty() && selected_members.empty(); + } }; struct RTLIL::Design { |