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author | Clifford Wolf <clifford@clifford.at> | 2014-07-26 21:16:05 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-07-26 21:30:38 +0200 |
commit | d68c993ed2ea384db4d6af5161b3b36096828499 (patch) | |
tree | 4f1259436d3d8f73eb21f1a29662826a24cedf4c /kernel | |
parent | 946ddff9cef3ea0b4dad8664319fb13074133775 (diff) | |
download | yosys-d68c993ed2ea384db4d6af5161b3b36096828499.tar.gz yosys-d68c993ed2ea384db4d6af5161b3b36096828499.tar.bz2 yosys-d68c993ed2ea384db4d6af5161b3b36096828499.zip |
Changed more code to the new RTLIL::Wire constructors
Diffstat (limited to 'kernel')
-rw-r--r-- | kernel/rtlil.cc | 14 | ||||
-rw-r--r-- | kernel/rtlil.h | 16 |
2 files changed, 23 insertions, 7 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 930e8a719..240bbc6be 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -777,7 +777,7 @@ void RTLIL::Module::cloneInto(RTLIL::Module *new_mod) const new_mod->attributes = attributes; for (auto &it : wires) - new_mod->wires[it.first] = new RTLIL::Wire(*it.second); + new_mod->addWire(it.first, it.second); for (auto &it : memories) new_mod->memories[it.first] = new RTLIL::Memory(*it.second); @@ -952,6 +952,18 @@ RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, int width) return wire; } +RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *other) +{ + RTLIL::Wire *wire = addWire(name); + wire->width = other->width; + wire->start_offset = other->start_offset; + wire->port_id = other->port_id; + wire->port_input = other->port_input; + wire->port_output = other->port_output; + wire->attributes = other->attributes; + return wire; +} + RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, RTLIL::IdString type) { RTLIL::Cell *cell = new RTLIL::Cell; diff --git a/kernel/rtlil.h b/kernel/rtlil.h index f43e7b670..cbb612473 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -273,6 +273,11 @@ struct RTLIL::Design { struct RTLIL::Module { +protected: + void add(RTLIL::Wire *wire); + void add(RTLIL::Cell *cell); + +public: RTLIL::IdString name; std::set<RTLIL::IdString> avail_parameters; std::map<RTLIL::IdString, RTLIL::Wire*> wires; @@ -297,9 +302,6 @@ struct RTLIL::Module void cloneInto(RTLIL::Module *new_mod) const; virtual RTLIL::Module *clone() const; - void add(RTLIL::Wire *wire); - void add(RTLIL::Cell *cell); - // Removing wires is expensive. If you have to remove wires, remove them all at once. void remove(const std::set<RTLIL::Wire*> &wires); void remove(RTLIL::Cell *cell); @@ -309,6 +311,8 @@ struct RTLIL::Module void rename(RTLIL::IdString old_name, RTLIL::IdString new_name); RTLIL::Wire *addWire(RTLIL::IdString name, int width = 1); + RTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other); + RTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type); RTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other); @@ -445,7 +449,7 @@ struct RTLIL::Module struct RTLIL::Wire { -//protected: +protected: // use module->addWire() and module->remove() to create or destroy wires friend struct RTLIL::Module; Wire(); @@ -453,8 +457,8 @@ struct RTLIL::Wire public: // do not simply copy wires - //Wire(RTLIL::Wire &other) = delete; - //void operator=(RTLIL::Wire &other) = delete; + Wire(RTLIL::Wire &other) = delete; + void operator=(RTLIL::Wire &other) = delete; RTLIL::IdString name; int width, start_offset, port_id; |