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| author | Clifford Wolf <clifford@clifford.at> | 2013-03-03 20:53:24 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-03-03 20:53:24 +0100 |
| commit | d4680fd5a02bf09872080096ab106abbb6f7e519 (patch) | |
| tree | 00ea354a47161f8ed6184b58b14d166c8738356d /kernel | |
| parent | 40646d3516c27210fed90666e448c0915690e3a1 (diff) | |
| download | yosys-d4680fd5a02bf09872080096ab106abbb6f7e519.tar.gz yosys-d4680fd5a02bf09872080096ab106abbb6f7e519.tar.bz2 yosys-d4680fd5a02bf09872080096ab106abbb6f7e519.zip | |
Added design->select() api and use it in extract pass
Diffstat (limited to 'kernel')
| -rw-r--r-- | kernel/rtlil.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index b5338a33c..a0d7a1a37 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -212,6 +212,13 @@ struct RTLIL::Design { template<typename T1, typename T2> bool selected(T1 *module, T2 *member) { return selected_member(module->name, member->name); } + template<typename T1, typename T2> void select(T1 *module, T2 *member) { + if (selection_stack.size() > 0) { + RTLIL::Selection &sel = selection_stack.back(); + if (!sel.full_selection && sel.selected_modules.count(module->name) == 0) + sel.selected_members[module->name].insert(member->name); + } + } }; struct RTLIL::Module { |