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| author | Clifford Wolf <clifford@clifford.at> | 2015-02-24 22:31:30 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-02-24 22:31:30 +0100 |
| commit | 9ae21263f0de0c0011c7de290af3600ddeb51a34 (patch) | |
| tree | 3d2701e49ff3e8bd02ecdd3c606fd551b0eed05d /kernel | |
| parent | 81fa4e81a60ffee742c676ab68deefa15495aab9 (diff) | |
| download | yosys-9ae21263f0de0c0011c7de290af3600ddeb51a34.tar.gz yosys-9ae21263f0de0c0011c7de290af3600ddeb51a34.tar.bz2 yosys-9ae21263f0de0c0011c7de290af3600ddeb51a34.zip | |
Some cleanups in "clean"
Diffstat (limited to 'kernel')
| -rw-r--r-- | kernel/rtlil.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index dd40e2fba..1d0008f9d 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -807,6 +807,14 @@ struct RTLIL::Design bool selected_module(RTLIL::Module *mod) const; bool selected_whole_module(RTLIL::Module *mod) const; + RTLIL::Selection &selection() { + return selection_stack.back(); + } + + const RTLIL::Selection &selection() const { + return selection_stack.back(); + } + bool full_selection() const { return selection_stack.back().full_selection; } |