Merge branch 'eddie/script_from_wire' into eddie/xc7srl_cleanup

1 files changed, 6 insertions, 6 deletions

diff --git a/kernel/yosys.cc b/kernel/yosys.cc
index 7d4948881..f95c0127b 100644
--- a/kernel/yosys.cc
+++ b/kernel/yosys.cc
@@ -1259,7 +1259,7 @@ struct ScriptCmdPass : public Pass {
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
 		log("    script <filename> [<from_label>:<to_label>]\n");
-		log("    script -select [selection]\n");
+		log("    script -scriptwire [selection]\n");
 		log("\n");
 		log("This command executes the yosys commands in the specified file (default\n");
 		log("behaviour), or commands embedded in the constant text value connected to the\n");
@@ -1276,17 +1276,17 @@ struct ScriptCmdPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
 	{
-		bool select_mode = false;
+		bool scriptwire = false;
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++) {
-			if (args[argidx] == "-select") {
-				select_mode = true;
+			if (args[argidx] == "-scriptwire") {
+				scriptwire = true;
 				continue;
 			}
 			break;
 		}
-		if (select_mode) {
+		if (scriptwire) {
 			extra_args(args, argidx, design);
 
 			for (auto mod : design->selected_modules())
@@ -1299,7 +1299,7 @@ struct ScriptCmdPass : public Pass {
 					if (!c.second.is_fully_const())
 						log_error("RHS of selected wire %s.%s is not constant.\n", log_id(mod), log_id(w));
 					auto v = c.second.as_const();
-					Pass::call(design, v.decode_string());
+					Pass::call_on_module(design, mod, v.decode_string());
 				}
 		}
 		else if (args.size() < 2)