diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-10-26 20:33:10 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-10-26 20:33:10 +0100 |
| commit | 70b2efdb05f24eb7a9f3e2f456e5452fff94a15e (patch) | |
| tree | faf75a016ba15af55c022e056d346a5a98193831 /kernel | |
| parent | 26cbe4a4e56c0b95483b7568914d0402ef955b72 (diff) | |
| download | yosys-70b2efdb05f24eb7a9f3e2f456e5452fff94a15e.tar.gz yosys-70b2efdb05f24eb7a9f3e2f456e5452fff94a15e.tar.bz2 yosys-70b2efdb05f24eb7a9f3e2f456e5452fff94a15e.zip | |
Added support for $readmemh/$readmemb
Diffstat (limited to 'kernel')
| -rw-r--r-- | kernel/rtlil.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 1a9eb4d14..8cfc0c5f9 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -2935,7 +2935,7 @@ bool RTLIL::SigSpec::parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::stri if (netname.size() == 0) continue; - if ('0' <= netname[0] && netname[0] <= '9') { + if (('0' <= netname[0] && netname[0] <= '9') || netname[0] == '\'') { cover("kernel.rtlil.sigspec.parse.const"); AST::get_line_num = sigspec_parse_get_dummy_line_num; AST::AstNode *ast = VERILOG_FRONTEND::const2ast(netname); |