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author | Clifford Wolf <clifford@clifford.at> | 2018-08-15 14:05:38 +0200 |
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committer | GitHub <noreply@github.com> | 2018-08-15 14:05:38 +0200 |
commit | 67b10262975340e0b53f8d1072ac2e1c1f087fb1 (patch) | |
tree | c10a6e56f6f5b61ce3fbff7c165207cc40d704c8 /kernel | |
parent | d8e40c75eb96e7f3c995b2acd018b5cba6005cdd (diff) | |
parent | 3aa4484a3cd9a2e82fddd499cde575eaf8c565cc (diff) | |
download | yosys-67b10262975340e0b53f8d1072ac2e1c1f087fb1.tar.gz yosys-67b10262975340e0b53f8d1072ac2e1c1f087fb1.tar.bz2 yosys-67b10262975340e0b53f8d1072ac2e1c1f087fb1.zip |
Merge pull request #591 from hzeller/virtual-override
Consistent use of 'override' for virtual methods in derived classes.
Diffstat (limited to 'kernel')
-rw-r--r-- | kernel/celledges.h | 6 | ||||
-rw-r--r-- | kernel/modtools.h | 10 | ||||
-rw-r--r-- | kernel/register.cc | 11 | ||||
-rw-r--r-- | kernel/register.h | 14 | ||||
-rw-r--r-- | kernel/rtlil.h | 2 | ||||
-rw-r--r-- | kernel/satgen.h | 2 | ||||
-rw-r--r-- | kernel/yosys.cc | 16 | ||||
-rw-r--r-- | kernel/yosys.h | 2 |
8 files changed, 31 insertions, 32 deletions
diff --git a/kernel/celledges.h b/kernel/celledges.h index 6aab9ed43..2cc297cb2 100644 --- a/kernel/celledges.h +++ b/kernel/celledges.h @@ -1,4 +1,4 @@ -/* +/* -*- c++ -*- * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> @@ -38,7 +38,7 @@ struct FwdCellEdgesDatabase : AbstractCellEdgesDatabase dict<SigBit, pool<SigBit>> db; FwdCellEdgesDatabase(SigMap &sigmap) : sigmap(sigmap) { } - virtual void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) override { + void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) YS_OVERRIDE { SigBit from_sigbit = sigmap(cell->getPort(from_port)[from_bit]); SigBit to_sigbit = sigmap(cell->getPort(to_port)[to_bit]); db[from_sigbit].insert(to_sigbit); @@ -51,7 +51,7 @@ struct RevCellEdgesDatabase : AbstractCellEdgesDatabase dict<SigBit, pool<SigBit>> db; RevCellEdgesDatabase(SigMap &sigmap) : sigmap(sigmap) { } - virtual void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) override { + void add_edge(RTLIL::Cell *cell, RTLIL::IdString from_port, int from_bit, RTLIL::IdString to_port, int to_bit, int) YS_OVERRIDE { SigBit from_sigbit = sigmap(cell->getPort(from_port)[from_bit]); SigBit to_sigbit = sigmap(cell->getPort(to_port)[to_bit]); db[to_sigbit].insert(from_sigbit); diff --git a/kernel/modtools.h b/kernel/modtools.h index ffcb48d44..409562eb9 100644 --- a/kernel/modtools.h +++ b/kernel/modtools.h @@ -1,4 +1,4 @@ -/* +/* -*- c++ -*- * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> @@ -158,7 +158,7 @@ struct ModIndex : public RTLIL::Monitor #endif } - virtual void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, RTLIL::SigSpec &sig) YS_OVERRIDE + void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, RTLIL::SigSpec &sig) YS_OVERRIDE { log_assert(module == cell->module); @@ -169,7 +169,7 @@ struct ModIndex : public RTLIL::Monitor port_add(cell, port, sig); } - virtual void notify_connect(RTLIL::Module *mod YS_ATTRIBUTE(unused), const RTLIL::SigSig &sigsig) YS_OVERRIDE + void notify_connect(RTLIL::Module *mod YS_ATTRIBUTE(unused), const RTLIL::SigSig &sigsig) YS_OVERRIDE { log_assert(module == mod); @@ -214,13 +214,13 @@ struct ModIndex : public RTLIL::Monitor } } - virtual void notify_connect(RTLIL::Module *mod YS_ATTRIBUTE(unused), const std::vector<RTLIL::SigSig>&) YS_OVERRIDE + void notify_connect(RTLIL::Module *mod YS_ATTRIBUTE(unused), const std::vector<RTLIL::SigSig>&) YS_OVERRIDE { log_assert(module == mod); auto_reload_module = true; } - virtual void notify_blackout(RTLIL::Module *mod YS_ATTRIBUTE(unused)) YS_OVERRIDE + void notify_blackout(RTLIL::Module *mod YS_ATTRIBUTE(unused)) YS_OVERRIDE { log_assert(module == mod); auto_reload_module = true; diff --git a/kernel/register.cc b/kernel/register.cc index e30414f44..402a5b3ea 100644 --- a/kernel/register.cc +++ b/kernel/register.cc @@ -615,7 +615,7 @@ static struct CellHelpMessages { struct HelpPass : public Pass { HelpPass() : Pass("help", "display help messages") { } - virtual void help() + void help() YS_OVERRIDE { log("\n"); log(" help ................ list all commands\n"); @@ -684,7 +684,7 @@ struct HelpPass : public Pass { fclose(f); } - virtual void execute(std::vector<std::string> args, RTLIL::Design*) + void execute(std::vector<std::string> args, RTLIL::Design*) YS_OVERRIDE { if (args.size() == 1) { log("\n"); @@ -768,7 +768,7 @@ struct HelpPass : public Pass { struct EchoPass : public Pass { EchoPass() : Pass("echo", "turning echoing back of commands on and off") { } - virtual void help() + void help() YS_OVERRIDE { log("\n"); log(" echo on\n"); @@ -781,7 +781,7 @@ struct EchoPass : public Pass { log("Do not print all commands to log before executing them. (default)\n"); log("\n"); } - virtual void execute(std::vector<std::string> args, RTLIL::Design*) + void execute(std::vector<std::string> args, RTLIL::Design*) YS_OVERRIDE { if (args.size() > 2) cmd_error(args, 2, "Unexpected argument."); @@ -806,10 +806,9 @@ struct MinisatSatSolver : public SatSolver { MinisatSatSolver() : SatSolver("minisat") { yosys_satsolver = this; } - virtual ezSAT *create() YS_OVERRIDE { + ezSAT *create() YS_OVERRIDE { return new ezMiniSAT(); } } MinisatSatSolver; YOSYS_NAMESPACE_END - diff --git a/kernel/register.h b/kernel/register.h index 8024c56a0..c74029823 100644 --- a/kernel/register.h +++ b/kernel/register.h @@ -1,4 +1,4 @@ -/* +/* -*- c++ -*- * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> @@ -88,9 +88,9 @@ struct Frontend : Pass std::string frontend_name; Frontend(std::string name, std::string short_help = "** document me **"); - virtual void run_register() YS_OVERRIDE; - virtual ~Frontend(); - virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE YS_FINAL; + void run_register() YS_OVERRIDE; + ~Frontend() YS_OVERRIDE; + void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE YS_FINAL; virtual void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) = 0; static std::vector<std::string> next_args; @@ -104,9 +104,9 @@ struct Backend : Pass { std::string backend_name; Backend(std::string name, std::string short_help = "** document me **"); - virtual void run_register() YS_OVERRIDE; - virtual ~Backend(); - virtual void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE YS_FINAL; + void run_register() YS_OVERRIDE; + ~Backend() YS_OVERRIDE; + void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE YS_FINAL; virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) = 0; void extra_args(std::ostream *&f, std::string &filename, std::vector<std::string> args, size_t argidx); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 54d0b8c22..027faf416 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1,4 +1,4 @@ -/* +/* -*- c++ -*- * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> diff --git a/kernel/satgen.h b/kernel/satgen.h index 8d760fff7..210cca3f3 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -1,4 +1,4 @@ -/* +/* -*- c++ -*- * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> diff --git a/kernel/yosys.cc b/kernel/yosys.cc index dca277532..264b1f63d 100644 --- a/kernel/yosys.cc +++ b/kernel/yosys.cc @@ -636,7 +636,7 @@ extern Tcl_Interp *yosys_get_tcl_interp() struct TclPass : public Pass { TclPass() : Pass("tcl", "execute a TCL script file") { } - virtual void help() { + void help() YS_OVERRIDE { log("\n"); log(" tcl <filename>\n"); log("\n"); @@ -649,7 +649,7 @@ struct TclPass : public Pass { log("in order to avoid a name collision with the built in commands.\n"); log("\n"); } - virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { + void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE { if (args.size() < 2) log_cmd_error("Missing script file.\n"); if (args.size() > 2) @@ -1113,7 +1113,7 @@ void shell(RTLIL::Design *design) struct ShellPass : public Pass { ShellPass() : Pass("shell", "enter interactive command mode") { } - virtual void help() { + void help() YS_OVERRIDE { log("\n"); log(" shell\n"); log("\n"); @@ -1145,7 +1145,7 @@ struct ShellPass : public Pass { log("Press Ctrl-D or type 'exit' to leave the interactive shell.\n"); log("\n"); } - virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { + void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE { extra_args(args, 1, design, false); shell(design); } @@ -1154,7 +1154,7 @@ struct ShellPass : public Pass { #if defined(YOSYS_ENABLE_READLINE) || defined(YOSYS_ENABLE_EDITLINE) struct HistoryPass : public Pass { HistoryPass() : Pass("history", "show last interactive commands") { } - virtual void help() { + void help() YS_OVERRIDE { log("\n"); log(" history\n"); log("\n"); @@ -1163,7 +1163,7 @@ struct HistoryPass : public Pass { log("from executed scripts.\n"); log("\n"); } - virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { + void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE { extra_args(args, 1, design, false); #ifdef YOSYS_ENABLE_READLINE for(HIST_ENTRY **list = history_list(); *list != NULL; list++) @@ -1178,7 +1178,7 @@ struct HistoryPass : public Pass { struct ScriptCmdPass : public Pass { ScriptCmdPass() : Pass("script", "execute commands from script file") { } - virtual void help() { + void help() YS_OVERRIDE { log("\n"); log(" script <filename> [<from_label>:<to_label>]\n"); log("\n"); @@ -1193,7 +1193,7 @@ struct ScriptCmdPass : public Pass { log("marked with that label (until the next label) is executed.\n"); log("\n"); } - virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { + void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE { if (args.size() < 2) log_cmd_error("Missing script file.\n"); else if (args.size() == 2) diff --git a/kernel/yosys.h b/kernel/yosys.h index 14cbcd610..c9f973318 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -1,4 +1,4 @@ -/* +/* -*- c++ -*- * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> |