Use more ID::{A,B,Y,blackbox,whitebox}

8 files changed, 288 insertions, 286 deletions

diff --git a/kernel/cellaigs.cc b/kernel/cellaigs.cc
index 6d496db45..02854edb2 100644
--- a/kernel/cellaigs.cc
+++ b/kernel/cellaigs.cc
@@ -292,19 +292,19 @@ Aig::Aig(Cell *cell)
 
 	if (cell->type.in(ID($not), ID($_NOT_), ID($pos), ID($_BUF_)))
 	{
-		for (int i = 0; i < GetSize(cell->getPort(ID(Y))); i++) {
-			int A = mk.inport(ID(A), i);
+		for (int i = 0; i < GetSize(cell->getPort(ID::Y)); i++) {
+			int A = mk.inport(ID::A, i);
 			int Y = cell->type.in(ID($not), ID($_NOT_)) ? mk.not_gate(A) : A;
-			mk.outport(Y, ID(Y), i);
+			mk.outport(Y, ID::Y, i);
 		}
 		goto optimize;
 	}
 
 	if (cell->type.in(ID($and), ID($_AND_), ID($_NAND_), ID($or), ID($_OR_), ID($_NOR_), ID($xor), ID($xnor), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_)))
 	{
-		for (int i = 0; i < GetSize(cell->getPort(ID(Y))); i++) {
-			int A = mk.inport(ID(A), i);
-			int B = mk.inport(ID(B), i);
+		for (int i = 0; i < GetSize(cell->getPort(ID::Y)); i++) {
+			int A = mk.inport(ID::A, i);
+			int B = mk.inport(ID::B, i);
 			int Y = cell->type.in(ID($and), ID($_AND_))   ? mk.and_gate(A, B) :
 			        cell->type.in(ID($_NAND_))          ? mk.nand_gate(A, B) :
 			        cell->type.in(ID($or), ID($_OR_))     ? mk.or_gate(A, B) :
@@ -313,7 +313,7 @@ Aig::Aig(Cell *cell)
 			        cell->type.in(ID($xnor), ID($_XNOR_)) ? mk.xnor_gate(A, B) :
 			        cell->type.in(ID($_ANDNOT_))        ? mk.andnot_gate(A, B) :
 			        cell->type.in(ID($_ORNOT_))         ? mk.ornot_gate(A, B) : -1;
-			mk.outport(Y, ID(Y), i);
+			mk.outport(Y, ID::Y, i);
 		}
 		goto optimize;
 	}
@@ -321,22 +321,22 @@ Aig::Aig(Cell *cell)
 	if (cell->type.in(ID($mux), ID($_MUX_)))
 	{
 		int S = mk.inport(ID(S));
-		for (int i = 0; i < GetSize(cell->getPort(ID(Y))); i++) {
-			int A = mk.inport(ID(A), i);
-			int B = mk.inport(ID(B), i);
+		for (int i = 0; i < GetSize(cell->getPort(ID::Y)); i++) {
+			int A = mk.inport(ID::A, i);
+			int B = mk.inport(ID::B, i);
 			int Y = mk.mux_gate(A, B, S);
 			if (cell->type == ID($_NMUX_))
 				Y = mk.not_gate(Y);
-			mk.outport(Y, ID(Y), i);
+			mk.outport(Y, ID::Y, i);
 		}
 		goto optimize;
 	}
 
 	if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool)))
 	{
-		int Y = mk.inport(ID(A), 0);
-		for (int i = 1; i < GetSize(cell->getPort(ID(A))); i++) {
-			int A = mk.inport(ID(A), i);
+		int Y = mk.inport(ID::A, 0);
+		for (int i = 1; i < GetSize(cell->getPort(ID::A)); i++) {
+			int A = mk.inport(ID::A, i);
 			if (cell->type == ID($reduce_and))  Y = mk.and_gate(A, Y);
 			if (cell->type == ID($reduce_or))   Y = mk.or_gate(A, Y);
 			if (cell->type == ID($reduce_bool)) Y = mk.or_gate(A, Y);
@@ -345,35 +345,35 @@ Aig::Aig(Cell *cell)
 		}
 		if (cell->type == ID($reduce_xnor))
 			Y = mk.not_gate(Y);
-		mk.outport(Y, ID(Y), 0);
-		for (int i = 1; i < GetSize(cell->getPort(ID(Y))); i++)
-			mk.outport(mk.bool_node(false), ID(Y), i);
+		mk.outport(Y, ID::Y, 0);
+		for (int i = 1; i < GetSize(cell->getPort(ID::Y)); i++)
+			mk.outport(mk.bool_node(false), ID::Y, i);
 		goto optimize;
 	}
 
 	if (cell->type.in(ID($logic_not), ID($logic_and), ID($logic_or)))
 	{
-		int A = mk.inport(ID(A), 0), Y = -1;
-		for (int i = 1; i < GetSize(cell->getPort(ID(A))); i++)
-			A = mk.or_gate(mk.inport(ID(A), i), A);
+		int A = mk.inport(ID::A, 0), Y = -1;
+		for (int i = 1; i < GetSize(cell->getPort(ID::A)); i++)
+			A = mk.or_gate(mk.inport(ID::A, i), A);
 		if (cell->type.in(ID($logic_and), ID($logic_or))) {
-			int B = mk.inport(ID(B), 0);
-			for (int i = 1; i < GetSize(cell->getPort(ID(B))); i++)
-				B = mk.or_gate(mk.inport(ID(B), i), B);
+			int B = mk.inport(ID::B, 0);
+			for (int i = 1; i < GetSize(cell->getPort(ID::B)); i++)
+				B = mk.or_gate(mk.inport(ID::B, i), B);
 			if (cell->type == ID($logic_and)) Y = mk.and_gate(A, B);
 			if (cell->type == ID($logic_or))  Y = mk.or_gate(A, B);
 		} else {
 			if (cell->type == ID($logic_not)) Y = mk.not_gate(A);
 		}
-		mk.outport_bool(Y, ID(Y));
+		mk.outport_bool(Y, ID::Y);
 		goto optimize;
 	}
 
 	if (cell->type.in(ID($add), ID($sub)))
 	{
-		int width = GetSize(cell->getPort(ID(Y)));
-		vector<int> A = mk.inport_vec(ID(A), width);
-		vector<int> B = mk.inport_vec(ID(B), width);
+		int width = GetSize(cell->getPort(ID::Y));
+		vector<int> A = mk.inport_vec(ID::A, width);
+		vector<int> B = mk.inport_vec(ID::B, width);
 		int carry = mk.bool_node(false);
 		if (cell->type == ID($sub)) {
 			for (auto &n : B)
@@ -381,15 +381,15 @@ Aig::Aig(Cell *cell)
 			carry = mk.not_gate(carry);
 		}
 		vector<int> Y = mk.adder(A, B, carry);
-		mk.outport_vec(Y, ID(Y));
+		mk.outport_vec(Y, ID::Y);
 		goto optimize;
 	}
 
 	if (cell->type == ID($alu))
 	{
-		int width = GetSize(cell->getPort(ID(Y)));
-		vector<int> A = mk.inport_vec(ID(A), width);
-		vector<int> B = mk.inport_vec(ID(B), width);
+		int width = GetSize(cell->getPort(ID::Y));
+		vector<int> A = mk.inport_vec(ID::A, width);
+		vector<int> B = mk.inport_vec(ID::B, width);
 		int carry = mk.inport(ID(CI));
 		int binv = mk.inport(ID(BI));
 		for (auto &n : B)
@@ -398,7 +398,7 @@ Aig::Aig(Cell *cell)
 		vector<int> Y = mk.adder(A, B, carry, &X, &CO);
 		for (int i = 0; i < width; i++)
 			X[i] = mk.xor_gate(A[i], B[i]);
-		mk.outport_vec(Y, ID(Y));
+		mk.outport_vec(Y, ID::Y);
 		mk.outport_vec(X, ID(X));
 		mk.outport_vec(CO, ID(CO));
 		goto optimize;
@@ -406,57 +406,57 @@ Aig::Aig(Cell *cell)
 
 	if (cell->type.in(ID($eq), ID($ne)))
 	{
-		int width = max(GetSize(cell->getPort(ID(A))), GetSize(cell->getPort(ID(B))));
-		vector<int> A = mk.inport_vec(ID(A), width);
-		vector<int> B = mk.inport_vec(ID(B), width);
+		int width = max(GetSize(cell->getPort(ID::A)), GetSize(cell->getPort(ID::B)));
+		vector<int> A = mk.inport_vec(ID::A, width);
+		vector<int> B = mk.inport_vec(ID::B, width);
 		int Y = mk.bool_node(false);
 		for (int i = 0; i < width; i++)
 			Y = mk.or_gate(Y, mk.xor_gate(A[i], B[i]));
 		if (cell->type == ID($eq))
 			Y = mk.not_gate(Y);
-		mk.outport_bool(Y, ID(Y));
+		mk.outport_bool(Y, ID::Y);
 		goto optimize;
 	}
 
 	if (cell->type == ID($_AOI3_))
 	{
-		int A = mk.inport(ID(A));
-		int B = mk.inport(ID(B));
+		int A = mk.inport(ID::A);
+		int B = mk.inport(ID::B);
 		int C = mk.inport(ID(C));
 		int Y = mk.nor_gate(mk.and_gate(A, B), C);
-		mk.outport(Y, ID(Y));
+		mk.outport(Y, ID::Y);
 		goto optimize;
 	}
 
 	if (cell->type == ID($_OAI3_))
 	{
-		int A = mk.inport(ID(A));
-		int B = mk.inport(ID(B));
+		int A = mk.inport(ID::A);
+		int B = mk.inport(ID::B);
 		int C = mk.inport(ID(C));
 		int Y = mk.nand_gate(mk.or_gate(A, B), C);
-		mk.outport(Y, ID(Y));
+		mk.outport(Y, ID::Y);
 		goto optimize;
 	}
 
 	if (cell->type == ID($_AOI4_))
 	{
-		int A = mk.inport(ID(A));
-		int B = mk.inport(ID(B));
+		int A = mk.inport(ID::A);
+		int B = mk.inport(ID::B);
 		int C = mk.inport(ID(C));
 		int D = mk.inport(ID(D));
 		int Y = mk.nor_gate(mk.and_gate(A, B), mk.and_gate(C, D));
-		mk.outport(Y, ID(Y));
+		mk.outport(Y, ID::Y);
 		goto optimize;
 	}
 
 	if (cell->type == ID($_OAI4_))
 	{
-		int A = mk.inport(ID(A));
-		int B = mk.inport(ID(B));
+		int A = mk.inport(ID::A);
+		int B = mk.inport(ID::B);
 		int C = mk.inport(ID(C));
 		int D = mk.inport(ID(D));
 		int Y = mk.nand_gate(mk.or_gate(A, B), mk.or_gate(C, D));
-		mk.outport(Y, ID(Y));
+		mk.outport(Y, ID::Y);
 		goto optimize;
 	}
 
diff --git a/kernel/celledges.cc b/kernel/celledges.cc
index 7a324a06e..d0bb99e83 100644
--- a/kernel/celledges.cc
+++ b/kernel/celledges.cc
@@ -24,7 +24,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 void bitwise_unary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
 {
-	IdString A = ID(A), Y = ID(Y);
+	IdString A = ID::A, Y = ID::Y;
 
 	bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool();
 	int a_width = GetSize(cell->getPort(A));
@@ -41,7 +41,7 @@ void bitwise_unary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
 
 void bitwise_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
 {
-	IdString A = ID(A), B = ID(B), Y = ID(Y);
+	IdString A = ID::A, B = ID::B, Y = ID::Y;
 
 	bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool();
 	int a_width = GetSize(cell->getPort(A));
@@ -71,7 +71,7 @@ void bitwise_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
 
 void arith_neg_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
 {
-	IdString A = ID(A), Y = ID(Y);
+	IdString A = ID::A, Y = ID::Y;
 
 	bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool();
 	int a_width = GetSize(cell->getPort(A));
@@ -87,7 +87,7 @@ void arith_neg_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
 
 void arith_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
 {
-	IdString A = ID(A), B = ID(B), Y = ID(Y);
+	IdString A = ID::A, B = ID::B, Y = ID::Y;
 
 	bool is_signed = cell->getParam(ID(A_SIGNED)).as_bool();
 	int a_width = GetSize(cell->getPort(A));
@@ -114,7 +114,7 @@ void arith_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
 
 void reduce_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
 {
-	IdString A = ID(A), Y = ID(Y);
+	IdString A = ID::A, Y = ID::Y;
 
 	int a_width = GetSize(cell->getPort(A));
 
@@ -124,7 +124,7 @@ void reduce_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
 
 void compare_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
 {
-	IdString A = ID(A), B = ID(B), Y = ID(Y);
+	IdString A = ID::A, B = ID::B, Y = ID::Y;
 
 	int a_width = GetSize(cell->getPort(A));
 	int b_width = GetSize(cell->getPort(B));
@@ -138,7 +138,7 @@ void compare_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
 
 void mux_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
 {
-	IdString A = ID(A), B = ID(B), S = ID(S), Y = ID(Y);
+	IdString A = ID::A, B = ID::B, S = ID(S), Y = ID::Y;
 
 	int a_width = GetSize(cell->getPort(A));
 	int b_width = GetSize(cell->getPort(B));
diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index ade305e83..bc96fd602 100644
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -84,7 +84,7 @@ struct CellTypes
 	{
 		setup_internals_eval();
 
-		IdString A = ID(A), B = ID(B), EN = ID(EN), Y = ID(Y);
+		IdString A = ID::A, B = ID::B, EN = ID(EN), Y = ID::Y;
 		IdString SRC = ID(SRC), DST = ID(DST), DAT = ID(DAT);
 		IdString EN_SRC = ID(EN_SRC), EN_DST = ID(EN_DST);
 
@@ -121,7 +121,7 @@ struct CellTypes
 			ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($pow),
 			ID($logic_and), ID($logic_or), ID($concat), ID($macc)
 		};
-		IdString A = ID(A), B = ID(B), S = ID(S), Y = ID(Y);
+		IdString A = ID::A, B = ID::B, S = ID(S), Y = ID::Y;
 		IdString P = ID(P), G = ID(G), C = ID(C), X = ID(X);
 		IdString BI = ID(BI), CI = ID(CI), CO = ID(CO), EN = ID(EN);
 
@@ -177,19 +177,19 @@ struct CellTypes
 	{
 		setup_stdcells_eval();
 
-		IdString A = ID(A), E = ID(E), Y = ID(Y);
+		IdString A = ID::A, E = ID(E), Y = ID::Y;
 
 		setup_type(ID($_TBUF_), {A, E}, {Y}, true);
 	}
 
 	void setup_stdcells_eval()
 	{
-		IdString A = ID(A), B = ID(B), C = ID(C), D = ID(D);
+		IdString A = ID::A, B = ID::B, C = ID(C), D = ID(D);
 		IdString E = ID(E), F = ID(F), G = ID(G), H = ID(H);
 		IdString I = ID(I), J = ID(J), K = ID(K), L = ID(L);
 		IdString M = ID(M), N = ID(N), O = ID(O), P = ID(P);
 		IdString S = ID(S), T = ID(T), U = ID(U), V = ID(V);
-		IdString Y = ID(Y);
+		IdString Y = ID::Y;
 
 		setup_type(ID($_BUF_), {A}, {Y}, true);
 		setup_type(ID($_NOT_), {A}, {Y}, true);
diff --git a/kernel/consteval.h b/kernel/consteval.h
index 09b4c434b..7a83d28e7 100644
--- a/kernel/consteval.h
+++ b/kernel/consteval.h
@@ -128,8 +128,8 @@ struct ConstEval
 
 		RTLIL::SigSpec sig_a, sig_b, sig_s, sig_y;
 
-		log_assert(cell->hasPort(ID(Y)));
-		sig_y = values_map(assign_map(cell->getPort(ID(Y))));
+		log_assert(cell->hasPort(ID::Y));
+		sig_y = values_map(assign_map(cell->getPort(ID::Y)));
 		if (sig_y.is_fully_const())
 			return true;
 
@@ -139,11 +139,11 @@ struct ConstEval
 				return false;
 		}
 
-		if (cell->hasPort(ID(A)))
-			sig_a = cell->getPort(ID(A));
+		if (cell->hasPort(ID::A))
+			sig_a = cell->getPort(ID::A);
 
-		if (cell->hasPort(ID(B)))
-			sig_b = cell->getPort(ID(B));
+		if (cell->hasPort(ID::B))
+			sig_b = cell->getPort(ID::B);
 
 		if (cell->type.in(ID($mux), ID($pmux), ID($_MUX_), ID($_NMUX_)))
 		{
@@ -298,11 +298,11 @@ struct ConstEval
 					return false;
 			}
 
-			RTLIL::Const result(0, GetSize(cell->getPort(ID(Y))));
+			RTLIL::Const result(0, GetSize(cell->getPort(ID::Y)));
 			if (!macc.eval(result))
 				log_abort();
 
-			set(cell->getPort(ID(Y)), result);
+			set(cell->getPort(ID::Y), result);
 		}
 		else
 		{
diff --git a/kernel/macc.h b/kernel/macc.h
index e07e7e01a..371f6737d 100644
--- a/kernel/macc.h
+++ b/kernel/macc.h
@@ -99,10 +99,10 @@ struct Macc
 
 	void from_cell(RTLIL::Cell *cell)
 	{
-		RTLIL::SigSpec port_a = cell->getPort(ID(A));
+		RTLIL::SigSpec port_a = cell->getPort(ID::A);
 
 		ports.clear();
-		bit_ports = cell->getPort(ID(B));
+		bit_ports = cell->getPort(ID::B);
 
 		std::vector<RTLIL::State> config_bits = cell->getParam(ID(CONFIG)).bits;
 		int config_cursor = 0;
@@ -191,8 +191,8 @@ struct Macc
 			port_a.append(port.in_b);
 		}
 
-		cell->setPort(ID(A), port_a);
-		cell->setPort(ID(B), bit_ports);
+		cell->setPort(ID::A, port_a);
+		cell->setPort(ID::B, bit_ports);
 		cell->setParam(ID(CONFIG), config_bits);
 		cell->setParam(ID(CONFIG_WIDTH), GetSize(config_bits));
 		cell->setParam(ID(A_WIDTH), GetSize(port_a));
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index d01bd0c62..1d380135b 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -717,7 +717,7 @@ void RTLIL::Module::makeblackbox()
 	processes.clear();
 
 	remove(delwires);
-	set_bool_attribute(ID(blackbox));
+	set_bool_attribute(ID::blackbox);
 }
 
 void RTLIL::Module::reprocess_module(RTLIL::Design *, dict<RTLIL::IdString, RTLIL::Module *>)
@@ -845,8 +845,8 @@ namespace {
 
 			if (cell->type.in(ID($not), ID($pos), ID($neg))) {
 				param_bool(ID(A_SIGNED));
-				port(ID(A), param(ID(A_WIDTH)));
-				port(ID(Y), param(ID(Y_WIDTH)));
+				port(ID::A, param(ID(A_WIDTH)));
+				port(ID::Y, param(ID(Y_WIDTH)));
 				check_expected();
 				return;
 			}
@@ -854,17 +854,17 @@ namespace {
 			if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor))) {
 				param_bool(ID(A_SIGNED));
 				param_bool(ID(B_SIGNED));
-				port(ID(A), param(ID(A_WIDTH)));
-				port(ID(B), param(ID(B_WIDTH)));
-				port(ID(Y), param(ID(Y_WIDTH)));
+				port(ID::A, param(ID(A_WIDTH)));
+				port(ID::B, param(ID(B_WIDTH)));
+				port(ID::Y, param(ID(Y_WIDTH)));
 				check_expected();
 				return;
 			}
 
 			if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool))) {
 				param_bool(ID(A_SIGNED));
-				port(ID(A), param(ID(A_WIDTH)));
-				port(ID(Y), param(ID(Y_WIDTH)));
+				port(ID::A, param(ID(A_WIDTH)));
+				port(ID::Y, param(ID(Y_WIDTH)));
 				check_expected();
 				return;
 			}
@@ -872,9 +872,9 @@ namespace {
 			if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx))) {
 				param_bool(ID(A_SIGNED));
 				param_bool(ID(B_SIGNED));
-				port(ID(A), param(ID(A_WIDTH)));
-				port(ID(B), param(ID(B_WIDTH)));
-				port(ID(Y), param(ID(Y_WIDTH)));
+				port(ID::A, param(ID(A_WIDTH)));
+				port(ID::B, param(ID(B_WIDTH)));
+				port(ID::Y, param(ID(Y_WIDTH)));
 				check_expected(false);
 				return;
 			}
@@ -882,9 +882,9 @@ namespace {
 			if (cell->type.in(ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt))) {
 				param_bool(ID(A_SIGNED));
 				param_bool(ID(B_SIGNED));
-				port(ID(A), param(ID(A_WIDTH)));
-				port(ID(B), param(ID(B_WIDTH)));
-				port(ID(Y), param(ID(Y_WIDTH)));
+				port(ID::A, param(ID(A_WIDTH)));
+				port(ID::B, param(ID(B_WIDTH)));
+				port(ID::Y, param(ID(Y_WIDTH)));
 				check_expected();
 				return;
 			}
@@ -892,19 +892,19 @@ namespace {
 			if (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($pow))) {
 				param_bool(ID(A_SIGNED));
 				param_bool(ID(B_SIGNED));
-				port(ID(A), param(ID(A_WIDTH)));
-				port(ID(B), param(ID(B_WIDTH)));
-				port(ID(Y), param(ID(Y_WIDTH)));
+				port(ID::A, param(ID(A_WIDTH)));
+				port(ID::B, param(ID(B_WIDTH)));
+				port(ID::Y, param(ID(Y_WIDTH)));
 				check_expected(cell->type != ID($pow));
 				return;
 			}
 
 			if (cell->type == ID($fa)) {
-				port(ID(A), param(ID(WIDTH)));
-				port(ID(B), param(ID(WIDTH)));
+				port(ID::A, param(ID(WIDTH)));
+				port(ID::B, param(ID(WIDTH)));
 				port(ID(C), param(ID(WIDTH)));
 				port(ID(X), param(ID(WIDTH)));
-				port(ID(Y), param(ID(WIDTH)));
+				port(ID::Y, param(ID(WIDTH)));
 				check_expected();
 				return;
 			}
@@ -921,12 +921,12 @@ namespace {
 			if (cell->type == ID($alu)) {
 				param_bool(ID(A_SIGNED));
 				param_bool(ID(B_SIGNED));
-				port(ID(A), param(ID(A_WIDTH)));
-				port(ID(B), param(ID(B_WIDTH)));
+				port(ID::A, param(ID(A_WIDTH)));
+				port(ID::B, param(ID(B_WIDTH)));
 				port(ID(CI), 1);
 				port(ID(BI), 1);
 				port(ID(X), param(ID(Y_WIDTH)));
-				port(ID(Y), param(ID(Y_WIDTH)));
+				port(ID::Y, param(ID(Y_WIDTH)));
 				port(ID(CO), param(ID(Y_WIDTH)));
 				check_expected();
 				return;
@@ -935,9 +935,9 @@ namespace {
 			if (cell->type == ID($macc)) {
 				param(ID(CONFIG));
 				param(ID(CONFIG_WIDTH));
-				port(ID(A), param(ID(A_WIDTH)));
-				port(ID(B), param(ID(B_WIDTH)));
-				port(ID(Y), param(ID(Y_WIDTH)));
+				port(ID::A, param(ID(A_WIDTH)));
+				port(ID::B, param(ID(B_WIDTH)));
+				port(ID::Y, param(ID(Y_WIDTH)));
 				check_expected();
 				Macc().from_cell(cell);
 				return;
@@ -945,8 +945,8 @@ namespace {
 
 			if (cell->type == ID($logic_not)) {
 				param_bool(ID(A_SIGNED));
-				port(ID(A), param(ID(A_WIDTH)));
-				port(ID(Y), param(ID(Y_WIDTH)));
+				port(ID::A, param(ID(A_WIDTH)));
+				port(ID::Y, param(ID(Y_WIDTH)));
 				check_expected();
 				return;
 			}
@@ -954,17 +954,17 @@ namespace {
 			if (cell->type.in(ID($logic_and), ID($logic_or))) {
 				param_bool(ID(A_SIGNED));
 				param_bool(ID(B_SIGNED));
-				port(ID(A), param(ID(A_WIDTH)));
-				port(ID(B), param(ID(B_WIDTH)));
-				port(ID(Y), param(ID(Y_WIDTH)));
+				port(ID::A, param(ID(A_WIDTH)));
+				port(ID::B, param(ID(B_WIDTH)));
+				port(ID::Y, param(ID(Y_WIDTH)));
 				check_expected(false);
 				return;
 			}
 
 			if (cell->type == ID($slice)) {
 				param(ID(OFFSET));
-				port(ID(A), param(ID(A_WIDTH)));
-				port(ID(Y), param(ID(Y_WIDTH)));
+				port(ID::A, param(ID(A_WIDTH)));
+				port(ID::Y, param(ID(Y_WIDTH)));
 				if (param(ID(OFFSET)) + param(ID(Y_WIDTH)) > param(ID(A_WIDTH)))
 					error(__LINE__);
 				check_expected();
@@ -972,35 +972,35 @@ namespace {
 			}
 
 			if (cell->type == ID($concat)) {
-				port(ID(A), param(ID(A_WIDTH)));
-				port(ID(B), param(ID(B_WIDTH)));
-				port(ID(Y), param(ID(A_WIDTH)) + param(ID(B_WIDTH)));
+				port(ID::A, param(ID(A_WIDTH)));
+				port(ID::B, param(ID(B_WIDTH)));
+				port(ID::Y, param(ID(A_WIDTH)) + param(ID(B_WIDTH)));
 				check_expected();
 				return;
 			}
 
 			if (cell->type == ID($mux)) {
-				port(ID(A), param(ID(WIDTH)));
-				port(ID(B), param(ID(WIDTH)));
+				port(ID::A, param(ID(WIDTH)));
+				port(ID::B, param(ID(WIDTH)));
 				port(ID(S), 1);
-				port(ID(Y), param(ID(WIDTH)));
+				port(ID::Y, param(ID(WIDTH)));
 				check_expected();
 				return;
 			}
 
 			if (cell->type == ID($pmux)) {
-				port(ID(A), param(ID(WIDTH)));
-				port(ID(B), param(ID(WIDTH)) * param(ID(S_WIDTH)));
+				port(ID::A, param(ID(WIDTH)));
+				port(ID::B, param(ID(WIDTH)) * param(ID(S_WIDTH)));
 				port(ID(S), param(ID(S_WIDTH)));
-				port(ID(Y), param(ID(WIDTH)));
+				port(ID::Y, param(ID(WIDTH)));
 				check_expected();
 				return;
 			}
 
 			if (cell->type == ID($lut)) {
 				param(ID(LUT));
-				port(ID(A), param(ID(WIDTH)));
-				port(ID(Y), 1);
+				port(ID::A, param(ID(WIDTH)));
+				port(ID::Y, 1);
 				check_expected();
 				return;
 			}
@@ -1008,8 +1008,8 @@ namespace {
 			if (cell->type == ID($sop)) {
 				param(ID(DEPTH));
 				param(ID(TABLE));
-				port(ID(A), param(ID(WIDTH)));
-				port(ID(Y), 1);
+				port(ID::A, param(ID(WIDTH)));
+				port(ID::Y, 1);
 				check_expected();
 				return;
 			}
@@ -1175,36 +1175,36 @@ namespace {
 			}
 
 			if (cell->type == ID($tribuf)) {
-				port(ID(A), param(ID(WIDTH)));
-				port(ID(Y), param(ID(WIDTH)));
+				port(ID::A, param(ID(WIDTH)));
+				port(ID::Y, param(ID(WIDTH)));
 				port(ID(EN), 1);
 				check_expected();
 				return;
 			}
 
 			if (cell->type.in(ID($assert), ID($assume), ID($live), ID($fair), ID($cover))) {
-				port(ID(A), 1);
+				port(ID::A, 1);
 				port(ID(EN), 1);
 				check_expected();
 				return;
 			}
 
 			if (cell->type == ID($initstate)) {
-				port(ID(Y), 1);
+				port(ID::Y, 1);
 				check_expected();
 				return;
 			}
 
 			if (cell->type.in(ID($anyconst), ID($anyseq), ID($allconst), ID($allseq))) {
-				port(ID(Y), param(ID(WIDTH)));
+				port(ID::Y, param(ID(WIDTH)));
 				check_expected();
 				return;
 			}
 
 			if (cell->type == ID($equiv)) {
-				port(ID(A), 1);
-				port(ID(B), 1);
-				port(ID(Y), 1);
+				port(ID::A, 1);
+				port(ID::B, 1);
+				port(ID::Y, 1);
 				check_expected();
 				return;
 			}
@@ -1831,8 +1831,8 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *oth
 		cell->parameters[ID(A_SIGNED)] = is_signed;         \
 		cell->parameters[ID(A_WIDTH)] = sig_a.size();       \
 		cell->parameters[ID(Y_WIDTH)] = sig_y.size();       \
-		cell->setPort(ID(A), sig_a);                        \
-		cell->setPort(ID(Y), sig_y);                        \
+		cell->setPort(ID::A, sig_a);                        \
+		cell->setPort(ID::Y, sig_y);                        \
 		cell->set_src_attribute(src);                       \
 		return cell;                                        \
 	} \
@@ -1860,9 +1860,9 @@ DEF_METHOD(LogicNot,   1, ID($logic_not))
 		cell->parameters[ID(A_WIDTH)] = sig_a.size();       \
 		cell->parameters[ID(B_WIDTH)] = sig_b.size();       \
 		cell->parameters[ID(Y_WIDTH)] = sig_y.size();       \
-		cell->setPort(ID(A), sig_a);                        \
-		cell->setPort(ID(B), sig_b);                        \
-		cell->setPort(ID(Y), sig_y);                        \
+		cell->setPort(ID::A, sig_a);                        \
+		cell->setPort(ID::B, sig_b);                        \
+		cell->setPort(ID::Y, sig_y);                        \
 		cell->set_src_attribute(src);                       \
 		return cell;                                        \
 	} \
@@ -1903,10 +1903,10 @@ DEF_METHOD(LogicOr,  1, ID($logic_or))
 		RTLIL::Cell *cell = addCell(name, _type);                 \
 		cell->parameters[ID(WIDTH)] = sig_a.size();               \
 		if (_pmux) cell->parameters[ID(S_WIDTH)] = sig_s.size();  \
-		cell->setPort(ID(A), sig_a);                              \
-		cell->setPort(ID(B), sig_b);                              \
+		cell->setPort(ID::A, sig_a);                              \
+		cell->setPort(ID::B, sig_b);                              \
 		cell->setPort(ID(S), sig_s);                              \
-		cell->setPort(ID(Y), sig_y);                              \
+		cell->setPort(ID::Y, sig_y);                              \
 		cell->set_src_attribute(src);                             \
 		return cell;                                              \
 	} \
@@ -2006,9 +2006,9 @@ RTLIL::Cell* RTLIL::Module::addPow(RTLIL::IdString name, RTLIL::SigSpec sig_a, R
 	cell->parameters[ID(A_WIDTH)] = sig_a.size();
 	cell->parameters[ID(B_WIDTH)] = sig_b.size();
 	cell->parameters[ID(Y_WIDTH)] = sig_y.size();
-	cell->setPort(ID(A), sig_a);
-	cell->setPort(ID(B), sig_b);
-	cell->setPort(ID(Y), sig_y);
+	cell->setPort(ID::A, sig_a);
+	cell->setPort(ID::B, sig_b);
+	cell->setPort(ID::Y, sig_y);
 	cell->set_src_attribute(src);
 	return cell;
 }
@@ -2019,8 +2019,8 @@ RTLIL::Cell* RTLIL::Module::addSlice(RTLIL::IdString name, RTLIL::SigSpec sig_a,
 	cell->parameters[ID(A_WIDTH)] = sig_a.size();
 	cell->parameters[ID(Y_WIDTH)] = sig_y.size();
 	cell->parameters[ID(OFFSET)] = offset;
-	cell->setPort(ID(A), sig_a);
-	cell->setPort(ID(Y), sig_y);
+	cell->setPort(ID::A, sig_a);
+	cell->setPort(ID::Y, sig_y);
 	cell->set_src_attribute(src);
 	return cell;
 }
@@ -2030,9 +2030,9 @@ RTLIL::Cell* RTLIL::Module::addConcat(RTLIL::IdString name, RTLIL::SigSpec sig_a
 	RTLIL::Cell *cell = addCell(name, ID($concat));
 	cell->parameters[ID(A_WIDTH)] = sig_a.size();
 	cell->parameters[ID(B_WIDTH)] = sig_b.size();
-	cell->setPort(ID(A), sig_a);
-	cell->setPort(ID(B), sig_b);
-	cell->setPort(ID(Y), sig_y);
+	cell->setPort(ID::A, sig_a);
+	cell->setPort(ID::B, sig_b);
+	cell->setPort(ID::Y, sig_y);
 	cell->set_src_attribute(src);
 	return cell;
 }
@@ -2042,8 +2042,8 @@ RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_a, R
 	RTLIL::Cell *cell = addCell(name, ID($lut));
 	cell->parameters[ID(LUT)] = lut;
 	cell->parameters[ID(WIDTH)] = sig_a.size();
-	cell->setPort(ID(A), sig_a);
-	cell->setPort(ID(Y), sig_y);
+	cell->setPort(ID::A, sig_a);
+	cell->setPort(ID::Y, sig_y);
 	cell->set_src_attribute(src);
 	return cell;
 }
@@ -2052,9 +2052,9 @@ RTLIL::Cell* RTLIL::Module::addTribuf(RTLIL::IdString name, RTLIL::SigSpec sig_a
 {
 	RTLIL::Cell *cell = addCell(name, ID($tribuf));
 	cell->parameters[ID(WIDTH)] = sig_a.size();
-	cell->setPort(ID(A), sig_a);
+	cell->setPort(ID::A, sig_a);
 	cell->setPort(ID(EN), sig_en);
-	cell->setPort(ID(Y), sig_y);
+	cell->setPort(ID::Y, sig_y);
 	cell->set_src_attribute(src);
 	return cell;
 }
@@ -2062,7 +2062,7 @@ RTLIL::Cell* RTLIL::Module::addTribuf(RTLIL::IdString name, RTLIL::SigSpec sig_a
 RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
 {
 	RTLIL::Cell *cell = addCell(name, ID($assert));
-	cell->setPort(ID(A), sig_a);
+	cell->setPort(ID::A, sig_a);
 	cell->setPort(ID(EN), sig_en);
 	cell->set_src_attribute(src);
 	return cell;
@@ -2071,7 +2071,7 @@ RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a
 RTLIL::Cell* RTLIL::Module::addAssume(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
 {
 	RTLIL::Cell *cell = addCell(name, ID($assume));
-	cell->setPort(ID(A), sig_a);
+	cell->setPort(ID::A, sig_a);
 	cell->setPort(ID(EN), sig_en);
 	cell->set_src_attribute(src);
 	return cell;
@@ -2080,7 +2080,7 @@ RTLIL::Cell* RTLIL::Module::addAssume(RTLIL::IdString name, RTLIL::SigSpec sig_a
 RTLIL::Cell* RTLIL::Module::addLive(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
 {
 	RTLIL::Cell *cell = addCell(name, ID($live));
-	cell->setPort(ID(A), sig_a);
+	cell->setPort(ID::A, sig_a);
 	cell->setPort(ID(EN), sig_en);
 	cell->set_src_attribute(src);
 	return cell;
@@ -2089,7 +2089,7 @@ RTLIL::Cell* RTLIL::Module::addLive(RTLIL::IdString name, RTLIL::SigSpec sig_a,
 RTLIL::Cell* RTLIL::Module::addFair(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
 {
 	RTLIL::Cell *cell = addCell(name, ID($fair));
-	cell->setPort(ID(A), sig_a);
+	cell->setPort(ID::A, sig_a);
 	cell->setPort(ID(EN), sig_en);
 	cell->set_src_attribute(src);
 	return cell;
@@ -2098,7 +2098,7 @@ RTLIL::Cell* RTLIL::Module::addFair(RTLIL::IdString name, RTLIL::SigSpec sig_a,
 RTLIL::Cell* RTLIL::Module::addCover(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, const std::string &src)
 {
 	RTLIL::Cell *cell = addCell(name, ID($cover));
-	cell->setPort(ID(A), sig_a);
+	cell->setPort(ID::A, sig_a);
 	cell->setPort(ID(EN), sig_en);
 	cell->set_src_attribute(src);
 	return cell;
@@ -2107,9 +2107,9 @@ RTLIL::Cell* RTLIL::Module::addCover(RTLIL::IdString name, RTLIL::SigSpec sig_a,
 RTLIL::Cell* RTLIL::Module::addEquiv(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y, const std::string &src)
 {
 	RTLIL::Cell *cell = addCell(name, ID($equiv));
-	cell->setPort(ID(A), sig_a);
-	cell->setPort(ID(B), sig_b);
-	cell->setPort(ID(Y), sig_y);
+	cell->setPort(ID::A, sig_a);
+	cell->setPort(ID::B, sig_b);
+	cell->setPort(ID::Y, sig_y);
 	cell->set_src_attribute(src);
 	return cell;
 }
@@ -2308,7 +2308,7 @@ RTLIL::SigSpec RTLIL::Module::Anyconst(RTLIL::IdString name, int width, const st
 	RTLIL::SigSpec sig = addWire(NEW_ID, width);
 	Cell *cell = addCell(name, ID($anyconst));
 	cell->setParam(ID(WIDTH), width);
-	cell->setPort(ID(Y), sig);
+	cell->setPort(ID::Y, sig);
 	cell->set_src_attribute(src);
 	return sig;
 }
@@ -2318,7 +2318,7 @@ RTLIL::SigSpec RTLIL::Module::Anyseq(RTLIL::IdString name, int width, const std:
 	RTLIL::SigSpec sig = addWire(NEW_ID, width);
 	Cell *cell = addCell(name, ID($anyseq));
 	cell->setParam(ID(WIDTH), width);
-	cell->setPort(ID(Y), sig);
+	cell->setPort(ID::Y, sig);
 	cell->set_src_attribute(src);
 	return sig;
 }
@@ -2328,7 +2328,7 @@ RTLIL::SigSpec RTLIL::Module::Allconst(RTLIL::IdString name, int width, const st
 	RTLIL::SigSpec sig = addWire(NEW_ID, width);
 	Cell *cell = addCell(name, ID($allconst));
 	cell->setParam(ID(WIDTH), width);
-	cell->setPort(ID(Y), sig);
+	cell->setPort(ID::Y, sig);
 	cell->set_src_attribute(src);
 	return sig;
 }
@@ -2338,7 +2338,7 @@ RTLIL::SigSpec RTLIL::Module::Allseq(RTLIL::IdString name, int width, const std:
 	RTLIL::SigSpec sig = addWire(NEW_ID, width);
 	Cell *cell = addCell(name, ID($allseq));
 	cell->setParam(ID(WIDTH), width);
-	cell->setPort(ID(Y), sig);
+	cell->setPort(ID::Y, sig);
 	cell->set_src_attribute(src);
 	return sig;
 }
@@ -2347,7 +2347,7 @@ RTLIL::SigSpec RTLIL::Module::Initstate(RTLIL::IdString name, const std::string
 {
 	RTLIL::SigSpec sig = addWire(NEW_ID);
 	Cell *cell = addCell(name, ID($initstate));
-	cell->setPort(ID(Y), sig);
+	cell->setPort(ID::Y, sig);
 	cell->set_src_attribute(src);
 	return sig;
 }
@@ -2569,7 +2569,7 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
 		return;
 
 	if (type == ID($mux) || type == ID($pmux)) {
-		parameters[ID(WIDTH)] = GetSize(connections_[ID(Y)]);
+		parameters[ID(WIDTH)] = GetSize(connections_[ID::Y]);
 		if (type == ID($pmux))
 			parameters[ID(S_WIDTH)] = GetSize(connections_[ID(S)]);
 		check();
@@ -2577,12 +2577,12 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
 	}
 
 	if (type == ID($lut) || type == ID($sop)) {
-		parameters[ID(WIDTH)] = GetSize(connections_[ID(A)]);
+		parameters[ID(WIDTH)] = GetSize(connections_[ID::A]);
 		return;
 	}
 
 	if (type == ID($fa)) {
-		parameters[ID(WIDTH)] = GetSize(connections_[ID(Y)]);
+		parameters[ID(WIDTH)] = GetSize(connections_[ID::Y]);
 		return;
 	}
 
@@ -2593,28 +2593,28 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
 
 	bool signedness_ab = !type.in(ID($slice), ID($concat), ID($macc));
 
-	if (connections_.count(ID(A))) {
+	if (connections_.count(ID::A)) {
 		if (signedness_ab) {
 			if (set_a_signed)
 				parameters[ID(A_SIGNED)] = true;
 			else if (parameters.count(ID(A_SIGNED)) == 0)
 				parameters[ID(A_SIGNED)] = false;
 		}
-		parameters[ID(A_WIDTH)] = GetSize(connections_[ID(A)]);
+		parameters[ID(A_WIDTH)] = GetSize(connections_[ID::A]);
 	}
 
-	if (connections_.count(ID(B))) {
+	if (connections_.count(ID::B)) {
 		if (signedness_ab) {
 			if (set_b_signed)
 				parameters[ID(B_SIGNED)] = true;
 			else if (parameters.count(ID(B_SIGNED)) == 0)
 				parameters[ID(B_SIGNED)] = false;
 		}
-		parameters[ID(B_WIDTH)] = GetSize(connections_[ID(B)]);
+		parameters[ID(B_WIDTH)] = GetSize(connections_[ID::B]);
 	}
 
-	if (connections_.count(ID(Y)))
-		parameters[ID(Y_WIDTH)] = GetSize(connections_[ID(Y)]);
+	if (connections_.count(ID::Y))
+		parameters[ID(Y_WIDTH)] = GetSize(connections_[ID::Y]);
 
 	if (connections_.count(ID(Q)))
 		parameters[ID(WIDTH)] = GetSize(connections_[ID(Q)]);
diff --git a/kernel/satgen.h b/kernel/satgen.h
index aab3017c2..133389eee 100644
--- a/kernel/satgen.h
+++ b/kernel/satgen.h
@@ -281,9 +281,9 @@ struct SatGen
 
 		if (model_undef && (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod)) || is_arith_compare))
 		{
-			std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep);
-			std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep);
-			std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep);
+			std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
+			std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
+			std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
 			if (is_arith_compare)
 				extendSignalWidth(undef_a, undef_b, cell, true);
 			else
@@ -294,7 +294,7 @@ struct SatGen
 			int undef_y_bit = ez->OR(undef_any_a, undef_any_b);
 
 			if (cell->type.in(ID($div), ID($mod))) {
-				std::vector<int> b = importSigSpec(cell->getPort(ID(B)), timestep);
+				std::vector<int> b = importSigSpec(cell->getPort(ID::B), timestep);
 				undef_y_bit = ez->OR(undef_y_bit, ez->NOT(ez->expression(ezSAT::OpOr, b)));
 			}
 
@@ -313,9 +313,9 @@ struct SatGen
 		if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_),
 				ID($and), ID($or), ID($xor), ID($xnor), ID($add), ID($sub)))
 		{
-			std::vector<int> a = importDefSigSpec(cell->getPort(ID(A)), timestep);
-			std::vector<int> b = importDefSigSpec(cell->getPort(ID(B)), timestep);
-			std::vector<int> y = importDefSigSpec(cell->getPort(ID(Y)), timestep);
+			std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
+			std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
+			std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
 			extendSignalWidth(a, b, y, cell);
 
 			std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
@@ -343,9 +343,9 @@ struct SatGen
 
 			if (model_undef && !arith_undef_handled)
 			{
-				std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep);
-				std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep);
-				std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep);
+				std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
+				std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
 				extendSignalWidth(undef_a, undef_b, undef_y, cell, false);
 
 				if (cell->type.in(ID($and), ID($_AND_), ID($_NAND_))) {
@@ -384,7 +384,7 @@ struct SatGen
 			}
 			else if (model_undef)
 			{
-				std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
 				undefGating(y, yy, undef_y);
 			}
 			return true;
@@ -395,11 +395,11 @@ struct SatGen
 			bool aoi_mode = cell->type.in(ID($_AOI3_), ID($_AOI4_));
 			bool three_mode = cell->type.in(ID($_AOI3_), ID($_OAI3_));
 
-			int a = importDefSigSpec(cell->getPort(ID(A)), timestep).at(0);
-			int b = importDefSigSpec(cell->getPort(ID(B)), timestep).at(0);
+			int a = importDefSigSpec(cell->getPort(ID::A), timestep).at(0);
+			int b = importDefSigSpec(cell->getPort(ID::B), timestep).at(0);
 			int c = importDefSigSpec(cell->getPort(ID(C)), timestep).at(0);
 			int d = three_mode ? (aoi_mode ? ez->CONST_TRUE : ez->CONST_FALSE) : importDefSigSpec(cell->getPort(ID(D)), timestep).at(0);
-			int y = importDefSigSpec(cell->getPort(ID(Y)), timestep).at(0);
+			int y = importDefSigSpec(cell->getPort(ID::Y), timestep).at(0);
 			int yy = model_undef ? ez->literal() : y;
 
 			if (cell->type.in(ID($_AOI3_), ID($_AOI4_)))
@@ -409,11 +409,11 @@ struct SatGen
 
 			if (model_undef)
 			{
-				int undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep).at(0);
-				int undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep).at(0);
+				int undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep).at(0);
+				int undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep).at(0);
 				int undef_c = importUndefSigSpec(cell->getPort(ID(C)), timestep).at(0);
 				int undef_d = three_mode ? ez->CONST_FALSE : importUndefSigSpec(cell->getPort(ID(D)), timestep).at(0);
-				int undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep).at(0);
+				int undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep).at(0);
 
 				if (aoi_mode)
 				{
@@ -458,16 +458,16 @@ struct SatGen
 
 		if (cell->type.in(ID($_NOT_), ID($not)))
 		{
-			std::vector<int> a = importDefSigSpec(cell->getPort(ID(A)), timestep);
-			std::vector<int> y = importDefSigSpec(cell->getPort(ID(Y)), timestep);
+			std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
+			std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
 			extendSignalWidthUnary(a, y, cell);
 
 			std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
 			ez->assume(ez->vec_eq(ez->vec_not(a), yy));
 
 			if (model_undef) {
-				std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep);
-				std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep);
+				std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
 				extendSignalWidthUnary(undef_a, undef_y, cell, false);
 				ez->assume(ez->vec_eq(undef_a, undef_y));
 				undefGating(y, yy, undef_y);
@@ -477,10 +477,10 @@ struct SatGen
 
 		if (cell->type.in(ID($_MUX_), ID($mux), ID($_NMUX_)))
 		{
-			std::vector<int> a = importDefSigSpec(cell->getPort(ID(A)), timestep);
-			std::vector<int> b = importDefSigSpec(cell->getPort(ID(B)), timestep);
+			std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
+			std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
 			std::vector<int> s = importDefSigSpec(cell->getPort(ID(S)), timestep);
-			std::vector<int> y = importDefSigSpec(cell->getPort(ID(Y)), timestep);
+			std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
 
 			std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
 			if (cell->type == ID($_NMUX_))
@@ -490,10 +490,10 @@ struct SatGen
 
 			if (model_undef)
 			{
-				std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep);
-				std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep);
+				std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
+				std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
 				std::vector<int> undef_s = importUndefSigSpec(cell->getPort(ID(S)), timestep);
-				std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
 
 				std::vector<int> unequal_ab = ez->vec_not(ez->vec_iff(a, b));
 				std::vector<int> undef_ab = ez->vec_or(unequal_ab, ez->vec_or(undef_a, undef_b));
@@ -506,10 +506,10 @@ struct SatGen
 
 		if (cell->type == ID($pmux))
 		{
-			std::vector<int> a = importDefSigSpec(cell->getPort(ID(A)), timestep);
-			std::vector<int> b = importDefSigSpec(cell->getPort(ID(B)), timestep);
+			std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
+			std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
 			std::vector<int> s = importDefSigSpec(cell->getPort(ID(S)), timestep);
-			std::vector<int> y = importDefSigSpec(cell->getPort(ID(Y)), timestep);
+			std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
 
 			std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
 
@@ -522,10 +522,10 @@ struct SatGen
 
 			if (model_undef)
 			{
-				std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep);
-				std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep);
+				std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
+				std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
 				std::vector<int> undef_s = importUndefSigSpec(cell->getPort(ID(S)), timestep);
-				std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
 
 				int maybe_a = ez->CONST_TRUE;
 
@@ -557,8 +557,8 @@ struct SatGen
 
 		if (cell->type.in(ID($pos), ID($neg)))
 		{
-			std::vector<int> a = importDefSigSpec(cell->getPort(ID(A)), timestep);
-			std::vector<int> y = importDefSigSpec(cell->getPort(ID(Y)), timestep);
+			std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
+			std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
 			extendSignalWidthUnary(a, y, cell);
 
 			std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
@@ -572,8 +572,8 @@ struct SatGen
 
 			if (model_undef)
 			{
-				std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep);
-				std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep);
+				std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
 				extendSignalWidthUnary(undef_a, undef_y, cell);
 
 				if (cell->type == ID($pos)) {
@@ -591,8 +591,8 @@ struct SatGen
 
 		if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool), ID($logic_not)))
 		{
-			std::vector<int> a = importDefSigSpec(cell->getPort(ID(A)), timestep);
-			std::vector<int> y = importDefSigSpec(cell->getPort(ID(Y)), timestep);
+			std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
+			std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
 
 			std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
 
@@ -611,8 +611,8 @@ struct SatGen
 
 			if (model_undef)
 			{
-				std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep);
-				std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep);
+				std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
 				int aX = ez->expression(ezSAT::OpOr, undef_a);
 
 				if (cell->type == ID($reduce_and)) {
@@ -638,12 +638,12 @@ struct SatGen
 
 		if (cell->type.in(ID($logic_and), ID($logic_or)))
 		{
-			std::vector<int> vec_a = importDefSigSpec(cell->getPort(ID(A)), timestep);
-			std::vector<int> vec_b = importDefSigSpec(cell->getPort(ID(B)), timestep);
+			std::vector<int> vec_a = importDefSigSpec(cell->getPort(ID::A), timestep);
+			std::vector<int> vec_b = importDefSigSpec(cell->getPort(ID::B), timestep);
 
 			int a = ez->expression(ez->OpOr, vec_a);
 			int b = ez->expression(ez->OpOr, vec_b);
-			std::vector<int> y = importDefSigSpec(cell->getPort(ID(Y)), timestep);
+			std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
 
 			std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
 
@@ -656,9 +656,9 @@ struct SatGen
 
 			if (model_undef)
 			{
-				std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep);
-				std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep);
-				std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep);
+				std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
+				std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
 
 				int a0 = ez->NOT(ez->OR(ez->expression(ezSAT::OpOr, vec_a), ez->expression(ezSAT::OpOr, undef_a)));
 				int b0 = ez->NOT(ez->OR(ez->expression(ezSAT::OpOr, vec_b), ez->expression(ezSAT::OpOr, undef_b)));
@@ -685,16 +685,16 @@ struct SatGen
 		if (cell->type.in(ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt)))
 		{
 			bool is_signed = cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool();
-			std::vector<int> a = importDefSigSpec(cell->getPort(ID(A)), timestep);
-			std::vector<int> b = importDefSigSpec(cell->getPort(ID(B)), timestep);
-			std::vector<int> y = importDefSigSpec(cell->getPort(ID(Y)), timestep);
+			std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
+			std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
+			std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
 			extendSignalWidth(a, b, cell);
 
 			std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
 
 			if (model_undef && cell->type.in(ID($eqx), ID($nex))) {
-				std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep);
-				std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep);
+				std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
+				std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
 				extendSignalWidth(undef_a, undef_b, cell, true);
 				a = ez->vec_or(a, undef_a);
 				b = ez->vec_or(b, undef_b);
@@ -717,9 +717,9 @@ struct SatGen
 
 			if (model_undef && cell->type.in(ID($eqx), ID($nex)))
 			{
-				std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep);
-				std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep);
-				std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep);
+				std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
+				std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
 				extendSignalWidth(undef_a, undef_b, cell, true);
 
 				if (cell->type == ID($eqx))
@@ -734,9 +734,9 @@ struct SatGen
 			}
 			else if (model_undef && cell->type.in(ID($eq), ID($ne)))
 			{
-				std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep);
-				std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep);
-				std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep);
+				std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
+				std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
 				extendSignalWidth(undef_a, undef_b, cell, true);
 
 				int undef_any_a = ez->expression(ezSAT::OpOr, undef_a);
@@ -758,7 +758,7 @@ struct SatGen
 			else
 			{
 				if (model_undef) {
-					std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep);
+					std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
 					undefGating(y, yy, undef_y);
 				}
 				log_assert(!model_undef || arith_undef_handled);
@@ -768,9 +768,9 @@ struct SatGen
 
 		if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx)))
 		{
-			std::vector<int> a = importDefSigSpec(cell->getPort(ID(A)), timestep);
-			std::vector<int> b = importDefSigSpec(cell->getPort(ID(B)), timestep);
-			std::vector<int> y = importDefSigSpec(cell->getPort(ID(Y)), timestep);
+			std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
+			std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
+			std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
 
 			int extend_bit = ez->CONST_FALSE;
 
@@ -801,9 +801,9 @@ struct SatGen
 
 			if (model_undef)
 			{
-				std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep);
-				std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep);
-				std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep);
+				std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
+				std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
 				std::vector<int> undef_a_shifted;
 
 				extend_bit = cell->type == ID($shiftx) ? ez->CONST_TRUE : ez->CONST_FALSE;
@@ -840,9 +840,9 @@ struct SatGen
 
 		if (cell->type == ID($mul))
 		{
-			std::vector<int> a = importDefSigSpec(cell->getPort(ID(A)), timestep);
-			std::vector<int> b = importDefSigSpec(cell->getPort(ID(B)), timestep);
-			std::vector<int> y = importDefSigSpec(cell->getPort(ID(Y)), timestep);
+			std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
+			std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
+			std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
 			extendSignalWidth(a, b, y, cell);
 
 			std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
@@ -859,7 +859,7 @@ struct SatGen
 
 			if (model_undef) {
 				log_assert(arith_undef_handled);
-				std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
 				undefGating(y, yy, undef_y);
 			}
 			return true;
@@ -867,9 +867,9 @@ struct SatGen
 
 		if (cell->type == ID($macc))
 		{
-			std::vector<int> a = importDefSigSpec(cell->getPort(ID(A)), timestep);
-			std::vector<int> b = importDefSigSpec(cell->getPort(ID(B)), timestep);
-			std::vector<int> y = importDefSigSpec(cell->getPort(ID(Y)), timestep);
+			std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
+			std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
+			std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
 
 			Macc macc;
 			macc.from_cell(cell);
@@ -918,13 +918,13 @@ struct SatGen
 
 			if (model_undef)
 			{
-				std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep);
-				std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep);
+				std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
+				std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
 
 				int undef_any_a = ez->expression(ezSAT::OpOr, undef_a);
 				int undef_any_b = ez->expression(ezSAT::OpOr, undef_b);
 
-				std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
 				ez->assume(ez->vec_eq(undef_y, std::vector<int>(GetSize(y), ez->OR(undef_any_a, undef_any_b))));
 
 				undefGating(y, tmp, undef_y);
@@ -937,9 +937,9 @@ struct SatGen
 
 		if (cell->type.in(ID($div), ID($mod)))
 		{
-			std::vector<int> a = importDefSigSpec(cell->getPort(ID(A)), timestep);
-			std::vector<int> b = importDefSigSpec(cell->getPort(ID(B)), timestep);
-			std::vector<int> y = importDefSigSpec(cell->getPort(ID(Y)), timestep);
+			std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
+			std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
+			std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
 			extendSignalWidth(a, b, y, cell);
 
 			std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
@@ -993,11 +993,11 @@ struct SatGen
 						only_first_one.at(0) = ez->CONST_TRUE;
 						div_zero_result = ez->vec_ite(a.back(), only_first_one, all_ones);
 					} else {
-						div_zero_result.insert(div_zero_result.end(), cell->getPort(ID(A)).size(), ez->CONST_TRUE);
+						div_zero_result.insert(div_zero_result.end(), cell->getPort(ID::A).size(), ez->CONST_TRUE);
 						div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), ez->CONST_FALSE);
 					}
 				} else {
-					int copy_a_bits = min(cell->getPort(ID(A)).size(), cell->getPort(ID(B)).size());
+					int copy_a_bits = min(cell->getPort(ID::A).size(), cell->getPort(ID::B).size());
 					div_zero_result.insert(div_zero_result.end(), a.begin(), a.begin() + copy_a_bits);
 					if (cell->parameters[ID(A_SIGNED)].as_bool() && cell->parameters[ID(B_SIGNED)].as_bool())
 						div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), div_zero_result.back());
@@ -1009,7 +1009,7 @@ struct SatGen
 
 			if (model_undef) {
 				log_assert(arith_undef_handled);
-				std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
 				undefGating(y, yy, undef_y);
 			}
 			return true;
@@ -1017,8 +1017,8 @@ struct SatGen
 
 		if (cell->type == ID($lut))
 		{
-			std::vector<int> a = importDefSigSpec(cell->getPort(ID(A)), timestep);
-			std::vector<int> y = importDefSigSpec(cell->getPort(ID(Y)), timestep);
+			std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
+			std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
 
 			std::vector<int> lut;
 			for (auto bit : cell->getParam(ID(LUT)).bits)
@@ -1029,7 +1029,7 @@ struct SatGen
 
 			if (model_undef)
 			{
-				std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep);
+				std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
 				std::vector<int> t(lut), u(GetSize(t), ez->CONST_FALSE);
 
 				for (int i = GetSize(a)-1; i >= 0; i--)
@@ -1047,7 +1047,7 @@ struct SatGen
 				log_assert(GetSize(t) == 1);
 				log_assert(GetSize(u) == 1);
 				undefGating(y, t, u);
-				ez->assume(ez->vec_eq(importUndefSigSpec(cell->getPort(ID(Y)), timestep), u));
+				ez->assume(ez->vec_eq(importUndefSigSpec(cell->getPort(ID::Y), timestep), u));
 			}
 			else
 			{
@@ -1067,8 +1067,8 @@ struct SatGen
 
 		if (cell->type == ID($sop))
 		{
-			std::vector<int> a = importDefSigSpec(cell->getPort(ID(A)), timestep);
-			int y = importDefSigSpec(cell->getPort(ID(Y)), timestep).at(0);
+			std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
+			int y = importDefSigSpec(cell->getPort(ID::Y), timestep).at(0);
 
 			int width = cell->getParam(ID(WIDTH)).as_int();
 			int depth = cell->getParam(ID(DEPTH)).as_int();
@@ -1096,8 +1096,8 @@ struct SatGen
 			if (model_undef)
 			{
 				std::vector<int> products, undef_products;
-				std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep);
-				int undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep).at(0);
+				std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
+				int undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep).at(0);
 
 				for (int i = 0; i < depth; i++)
 				{
@@ -1149,10 +1149,10 @@ struct SatGen
 
 		if (cell->type == ID($fa))
 		{
-			std::vector<int> a = importDefSigSpec(cell->getPort(ID(A)), timestep);
-			std::vector<int> b = importDefSigSpec(cell->getPort(ID(B)), timestep);
+			std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
+			std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
 			std::vector<int> c = importDefSigSpec(cell->getPort(ID(C)), timestep);
-			std::vector<int> y = importDefSigSpec(cell->getPort(ID(Y)), timestep);
+			std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
 			std::vector<int> x = importDefSigSpec(cell->getPort(ID(X)), timestep);
 
 			std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
@@ -1167,11 +1167,11 @@ struct SatGen
 
 			if (model_undef)
 			{
-				std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep);
-				std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep);
+				std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
+				std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
 				std::vector<int> undef_c = importUndefSigSpec(cell->getPort(ID(C)), timestep);
 
-				std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
 				std::vector<int> undef_x = importUndefSigSpec(cell->getPort(ID(X)), timestep);
 
 				ez->assume(ez->vec_eq(undef_y, ez->vec_or(ez->vec_or(undef_a, undef_b), undef_c)));
@@ -1217,9 +1217,9 @@ struct SatGen
 
 		if (cell->type == ID($alu))
 		{
-			std::vector<int> a = importDefSigSpec(cell->getPort(ID(A)), timestep);
-			std::vector<int> b = importDefSigSpec(cell->getPort(ID(B)), timestep);
-			std::vector<int> y = importDefSigSpec(cell->getPort(ID(Y)), timestep);
+			std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
+			std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
+			std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
 			std::vector<int> x = importDefSigSpec(cell->getPort(ID(X)), timestep);
 			std::vector<int> ci = importDefSigSpec(cell->getPort(ID(CI)), timestep);
 			std::vector<int> bi = importDefSigSpec(cell->getPort(ID(BI)), timestep);
@@ -1248,12 +1248,12 @@ struct SatGen
 
 			if (model_undef)
 			{
-				std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep);
-				std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID(B)), timestep);
+				std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
+				std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
 				std::vector<int> undef_ci = importUndefSigSpec(cell->getPort(ID(CI)), timestep);
 				std::vector<int> undef_bi = importUndefSigSpec(cell->getPort(ID(BI)), timestep);
 
-				std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
 				std::vector<int> undef_x = importUndefSigSpec(cell->getPort(ID(X)), timestep);
 				std::vector<int> undef_co = importUndefSigSpec(cell->getPort(ID(CO)), timestep);
 
@@ -1283,17 +1283,17 @@ struct SatGen
 
 		if (cell->type == ID($slice))
 		{
-			RTLIL::SigSpec a = cell->getPort(ID(A));
-			RTLIL::SigSpec y = cell->getPort(ID(Y));
+			RTLIL::SigSpec a = cell->getPort(ID::A);
+			RTLIL::SigSpec y = cell->getPort(ID::Y);
 			ez->assume(signals_eq(a.extract(cell->parameters.at(ID(OFFSET)).as_int(), y.size()), y, timestep));
 			return true;
 		}
 
 		if (cell->type == ID($concat))
 		{
-			RTLIL::SigSpec a = cell->getPort(ID(A));
-			RTLIL::SigSpec b = cell->getPort(ID(B));
-			RTLIL::SigSpec y = cell->getPort(ID(Y));
+			RTLIL::SigSpec a = cell->getPort(ID::A);
+			RTLIL::SigSpec b = cell->getPort(ID::B);
+			RTLIL::SigSpec y = cell->getPort(ID::Y);
 
 			RTLIL::SigSpec ab = a;
 			ab.append(b);
@@ -1333,16 +1333,16 @@ struct SatGen
 			if (timestep < 2)
 				return true;
 
-			std::vector<int> d = importDefSigSpec(cell->getPort(ID(Y)), timestep-1);
-			std::vector<int> q = importDefSigSpec(cell->getPort(ID(Y)), timestep);
+			std::vector<int> d = importDefSigSpec(cell->getPort(ID::Y), timestep-1);
+			std::vector<int> q = importDefSigSpec(cell->getPort(ID::Y), timestep);
 
 			std::vector<int> qq = model_undef ? ez->vec_var(q.size()) : q;
 			ez->assume(ez->vec_eq(d, qq));
 
 			if (model_undef)
 			{
-				std::vector<int> undef_d = importUndefSigSpec(cell->getPort(ID(Y)), timestep-1);
-				std::vector<int> undef_q = importUndefSigSpec(cell->getPort(ID(Y)), timestep);
+				std::vector<int> undef_d = importUndefSigSpec(cell->getPort(ID::Y), timestep-1);
+				std::vector<int> undef_q = importUndefSigSpec(cell->getPort(ID::Y), timestep);
 
 				ez->assume(ez->vec_eq(undef_d, undef_q));
 				undefGating(q, qq, undef_q);
@@ -1357,16 +1357,16 @@ struct SatGen
 
 		if (cell->type.in(ID($_BUF_), ID($equiv)))
 		{
-			std::vector<int> a = importDefSigSpec(cell->getPort(ID(A)), timestep);
-			std::vector<int> y = importDefSigSpec(cell->getPort(ID(Y)), timestep);
+			std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
+			std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
 			extendSignalWidthUnary(a, y, cell);
 
 			std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
 			ez->assume(ez->vec_eq(a, yy));
 
 			if (model_undef) {
-				std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID(A)), timestep);
-				std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep);
+				std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
 				extendSignalWidthUnary(undef_a, undef_y, cell, false);
 				ez->assume(ez->vec_eq(undef_a, undef_y));
 				undefGating(y, yy, undef_y);
@@ -1380,12 +1380,12 @@ struct SatGen
 			if (initstates.count(key) == 0)
 				initstates[key] = false;
 
-			std::vector<int> y = importDefSigSpec(cell->getPort(ID(Y)), timestep);
+			std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
 			log_assert(GetSize(y) == 1);
 			ez->SET(y[0], initstates[key] ? ez->CONST_TRUE : ez->CONST_FALSE);
 
 			if (model_undef) {
-				std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID(Y)), timestep);
+				std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
 				log_assert(GetSize(undef_y) == 1);
 				ez->SET(undef_y[0], ez->CONST_FALSE);
 			}
@@ -1396,7 +1396,7 @@ struct SatGen
 		if (cell->type == ID($assert))
 		{
 			std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep));
-			asserts_a[pf].append((*sigmap)(cell->getPort(ID(A))));
+			asserts_a[pf].append((*sigmap)(cell->getPort(ID::A)));
 			asserts_en[pf].append((*sigmap)(cell->getPort(ID(EN))));
 			return true;
 		}
@@ -1404,7 +1404,7 @@ struct SatGen
 		if (cell->type == ID($assume))
 		{
 			std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep));
-			assumes_a[pf].append((*sigmap)(cell->getPort(ID(A))));
+			assumes_a[pf].append((*sigmap)(cell->getPort(ID::A)));
 			assumes_en[pf].append((*sigmap)(cell->getPort(ID(EN))));
 			return true;
 		}
diff --git a/kernel/yosys.h b/kernel/yosys.h
index 49716ed52..52e7b3383 100644
--- a/kernel/yosys.h
+++ b/kernel/yosys.h
@@ -210,6 +210,7 @@ namespace RTLIL {
 	struct Module;
 	struct Design;
 	struct Monitor;
+    namespace ID {}
 }
 
 namespace AST {
@@ -224,6 +225,7 @@ using RTLIL::Wire;
 using RTLIL::Cell;
 using RTLIL::Module;
 using RTLIL::Design;
+namespace ID = RTLIL::ID;
 
 namespace hashlib {
 	template<> struct hash_ops<RTLIL::Wire*> : hash_obj_ops {};