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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-06 16:18:18 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-06 16:18:18 -0700 |
| commit | 3486235338faa1377bb4e1a8981a45b4ee6edfa9 (patch) | |
| tree | 3b40a647ccbfd39e15baa824ae67c1281d100e86 /kernel | |
| parent | 43081337fa4a85cd4a1a007576eaf945816bd576 (diff) | |
| download | yosys-3486235338faa1377bb4e1a8981a45b4ee6edfa9.tar.gz yosys-3486235338faa1377bb4e1a8981a45b4ee6edfa9.tar.bz2 yosys-3486235338faa1377bb4e1a8981a45b4ee6edfa9.zip | |
Make liberal use of IdString.in()
Diffstat (limited to 'kernel')
| -rw-r--r-- | kernel/rtlil.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index ba8472ec1..42c65143d 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -940,7 +940,7 @@ namespace { return; } - if (cell->type == "$logic_and" || cell->type == "$logic_or") { + if (cell->type.in("$logic_and", "$logic_or")) { param_bool("\\A_SIGNED"); param_bool("\\B_SIGNED"); port("\\A", param("\\A_WIDTH")); |