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| author | Clifford Wolf <clifford@clifford.at> | 2017-12-12 21:48:31 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-12-12 21:48:31 +0100 |
| commit | 2b6307547f37c219a67fea6345249615aaa5fc9a (patch) | |
| tree | 008dd44c9fbd032316fb0729f9d062b3b2085c08 /kernel | |
| parent | 82d1fd77de31aece7b8a4f31fa53cb9dda2ec5f6 (diff) | |
| download | yosys-2b6307547f37c219a67fea6345249615aaa5fc9a.tar.gz yosys-2b6307547f37c219a67fea6345249615aaa5fc9a.tar.bz2 yosys-2b6307547f37c219a67fea6345249615aaa5fc9a.zip | |
Add SigSpec::is_fully_ones()
Diffstat (limited to 'kernel')
| -rw-r--r-- | kernel/rtlil.cc | 15 | ||||
| -rw-r--r-- | kernel/rtlil.h | 1 |
2 files changed, 16 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 8c3d2962c..7dc7107c1 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -3353,6 +3353,21 @@ bool RTLIL::SigSpec::is_fully_zero() const return true; } +bool RTLIL::SigSpec::is_fully_ones() const +{ + cover("kernel.rtlil.sigspec.is_fully_ones"); + + pack(); + for (auto it = chunks_.begin(); it != chunks_.end(); it++) { + if (it->width > 0 && it->wire != NULL) + return false; + for (size_t i = 0; i < it->data.size(); i++) + if (it->data[i] != RTLIL::State::S1) + return false; + } + return true; +} + bool RTLIL::SigSpec::is_fully_def() const { cover("kernel.rtlil.sigspec.is_fully_def"); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 6ce9b6748..b33cb53a3 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -704,6 +704,7 @@ public: bool is_fully_const() const; bool is_fully_zero() const; + bool is_fully_ones() const; bool is_fully_def() const; bool is_fully_undef() const; bool has_const() const; |