diff options
| author | Clifford Wolf <clifford@clifford.at> | 2018-02-23 19:37:00 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-02-23 19:37:00 +0100 |
| commit | 0d636964b81ed5db4a7031a24c4b04e3bc879ad5 (patch) | |
| tree | 30ec1719eadc3d0a991e0b94e54a3c1a623c66d9 /kernel | |
| parent | 2521ed305e9d48929c9ede93b8cb0069739408f5 (diff) | |
| parent | b13e6bd375dc19fc2d6a3e67cdc6c045da732200 (diff) | |
| download | yosys-0d636964b81ed5db4a7031a24c4b04e3bc879ad5.tar.gz yosys-0d636964b81ed5db4a7031a24c4b04e3bc879ad5.tar.bz2 yosys-0d636964b81ed5db4a7031a24c4b04e3bc879ad5.zip | |
Merge branch 'forall'
Diffstat (limited to 'kernel')
| -rw-r--r-- | kernel/celltypes.h | 2 | ||||
| -rw-r--r-- | kernel/rtlil.cc | 22 | ||||
| -rw-r--r-- | kernel/rtlil.h | 2 |
3 files changed, 25 insertions, 1 deletions
diff --git a/kernel/celltypes.h b/kernel/celltypes.h index 5218b5363..fcc4fcc4b 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -122,6 +122,8 @@ struct CellTypes setup_type("$initstate", pool<RTLIL::IdString>(), {Y}, true); setup_type("$anyconst", pool<RTLIL::IdString>(), {Y}, true); setup_type("$anyseq", pool<RTLIL::IdString>(), {Y}, true); + setup_type("$allconst", pool<RTLIL::IdString>(), {Y}, true); + setup_type("$allseq", pool<RTLIL::IdString>(), {Y}, true); setup_type("$equiv", {A, B}, {Y}, true); } diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index fb3d9dbe9..a4fa2cf04 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1101,7 +1101,7 @@ namespace { return; } - if (cell->type.in("$anyconst", "$anyseq")) { + if (cell->type.in("$anyconst", "$anyseq", "$allconst", "$allseq")) { port("\\Y", param("\\WIDTH")); check_expected(); return; @@ -2145,6 +2145,26 @@ RTLIL::SigSpec RTLIL::Module::Anyseq(RTLIL::IdString name, int width, const std: return sig; } +RTLIL::SigSpec RTLIL::Module::Allconst(RTLIL::IdString name, int width, const std::string &src) +{ + RTLIL::SigSpec sig = addWire(NEW_ID, width); + Cell *cell = addCell(name, "$allconst"); + cell->setParam("\\WIDTH", width); + cell->setPort("\\Y", sig); + cell->set_src_attribute(src); + return sig; +} + +RTLIL::SigSpec RTLIL::Module::Allseq(RTLIL::IdString name, int width, const std::string &src) +{ + RTLIL::SigSpec sig = addWire(NEW_ID, width); + Cell *cell = addCell(name, "$allseq"); + cell->setParam("\\WIDTH", width); + cell->setPort("\\Y", sig); + cell->set_src_attribute(src); + return sig; +} + RTLIL::SigSpec RTLIL::Module::Initstate(RTLIL::IdString name, const std::string &src) { RTLIL::SigSpec sig = addWire(NEW_ID); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index a251b4252..54d0b8c22 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1127,6 +1127,8 @@ public: RTLIL::SigSpec Anyconst (RTLIL::IdString name, int width = 1, const std::string &src = ""); RTLIL::SigSpec Anyseq (RTLIL::IdString name, int width = 1, const std::string &src = ""); + RTLIL::SigSpec Allconst (RTLIL::IdString name, int width = 1, const std::string &src = ""); + RTLIL::SigSpec Allseq (RTLIL::IdString name, int width = 1, const std::string &src = ""); RTLIL::SigSpec Initstate (RTLIL::IdString name, const std::string &src = ""); }; |