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author | Clifford Wolf <clifford@clifford.at> | 2014-08-07 22:37:01 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-08-07 22:37:01 +0200 |
commit | 0b8b8d41eb07fd048cbe68acfe4b724e314bbb41 (patch) | |
tree | 08e61af3f963d66dfa2387a560bf65af30ece168 /kernel | |
parent | c55eb8f8a6c83514c5d46c6992c6c6fa1069a889 (diff) | |
download | yosys-0b8b8d41eb07fd048cbe68acfe4b724e314bbb41.tar.gz yosys-0b8b8d41eb07fd048cbe68acfe4b724e314bbb41.tar.bz2 yosys-0b8b8d41eb07fd048cbe68acfe4b724e314bbb41.zip |
Fixed build with gcc-4.6
Diffstat (limited to 'kernel')
-rw-r--r-- | kernel/modtools.h | 2 | ||||
-rw-r--r-- | kernel/register.h | 4 | ||||
-rw-r--r-- | kernel/yosys.h | 8 |
3 files changed, 11 insertions, 3 deletions
diff --git a/kernel/modtools.h b/kernel/modtools.h index fde59d142..58cdd5b0e 100644 --- a/kernel/modtools.h +++ b/kernel/modtools.h @@ -102,7 +102,7 @@ struct ModIndex : public RTLIL::Monitor auto_reload_module = false; } - virtual void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, RTLIL::SigSpec &sig) override + virtual void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, RTLIL::SigSpec &sig) OVERRIDE { if (auto_reload_module) reload_module(); diff --git a/kernel/register.h b/kernel/register.h index 93a3308ad..d7e4281c2 100644 --- a/kernel/register.h +++ b/kernel/register.h @@ -77,7 +77,7 @@ struct Frontend : Pass Frontend(std::string name, std::string short_help = "** document me **"); virtual void run_register(); virtual ~Frontend(); - virtual void execute(std::vector<std::string> args, RTLIL::Design *design) override final; + virtual void execute(std::vector<std::string> args, RTLIL::Design *design) OVERRIDE FINAL; virtual void execute(FILE *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) = 0; static std::vector<std::string> next_args; @@ -93,7 +93,7 @@ struct Backend : Pass Backend(std::string name, std::string short_help = "** document me **"); virtual void run_register(); virtual ~Backend(); - virtual void execute(std::vector<std::string> args, RTLIL::Design *design) override final; + virtual void execute(std::vector<std::string> args, RTLIL::Design *design) OVERRIDE FINAL; virtual void execute(FILE *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) = 0; void extra_args(FILE *&f, std::string &filename, std::vector<std::string> args, size_t argidx); diff --git a/kernel/yosys.h b/kernel/yosys.h index f9bbc0e44..e12069b4c 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -64,6 +64,14 @@ # define USING_YOSYS_NAMESPACE #endif +#if __cplusplus >= 201103L +# define OVERRIDE override +# define FINAL final +#else +# define OVERRIDE +# define FINAL +#endif + YOSYS_NAMESPACE_BEGIN namespace RTLIL { |