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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-06 15:24:55 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-06 15:24:55 -0700 |
| commit | 0b56be8c5634f8b953cd3d087b4b6e2a11a2c173 (patch) | |
| tree | 35fbcf4ce300bad6d0fa2facdc5bd0536f23b1c0 /kernel | |
| parent | 51b39219cda35e782fe4372409edf5432f86741f (diff) | |
| download | yosys-0b56be8c5634f8b953cd3d087b4b6e2a11a2c173.tar.gz yosys-0b56be8c5634f8b953cd3d087b4b6e2a11a2c173.tar.bz2 yosys-0b56be8c5634f8b953cd3d087b4b6e2a11a2c173.zip | |
Restore original SigSpec::extract()
Diffstat (limited to 'kernel')
| -rw-r--r-- | kernel/rtlil.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index f2c81db72..ba8472ec1 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -3355,7 +3355,7 @@ RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const { unpack(); cover("kernel.rtlil.sigspec.extract_pos"); - return std::vector<RTLIL::SigBit>(bits_.begin() + offset, length >= 0 ? bits_.begin() + offset + length : bits_.end() + length + 1); + return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length); } void RTLIL::SigSpec::append(const RTLIL::SigSpec &signal) |