Merge branch 'master' into eddie/pr1352

5 files changed, 16 insertions, 1 deletions

diff --git a/kernel/log.cc b/kernel/log.cc
index e0a60ca12..c5ba0d10d 100644
--- a/kernel/log.cc
+++ b/kernel/log.cc
@@ -551,6 +551,10 @@ void log_dump_val_worker(RTLIL::SigSpec v) {
 	log("%s", log_signal(v));
 }
 
+void log_dump_val_worker(RTLIL::State v) {
+	log("%s", log_signal(v));
+}
+
 const char *log_signal(const RTLIL::SigSpec &sig, bool autoint)
 {
 	std::stringstream buf;
diff --git a/kernel/log.h b/kernel/log.h
index 5f53f533a..1f15f3459 100644
--- a/kernel/log.h
+++ b/kernel/log.h
@@ -292,6 +292,7 @@ static inline void log_dump_val_worker(PerformanceTimer p) { log("%f seconds", p
 static inline void log_dump_args_worker(const char *p YS_ATTRIBUTE(unused)) { log_assert(*p == 0); }
 void log_dump_val_worker(RTLIL::IdString v);
 void log_dump_val_worker(RTLIL::SigSpec v);
+void log_dump_val_worker(RTLIL::State v);
 
 template<typename K, typename T, typename OPS>
 static inline void log_dump_val_worker(dict<K, T, OPS> &v) {
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 17be28f78..bd2fd91a3 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1528,7 +1528,7 @@ std::vector<RTLIL::Wire*> RTLIL::Module::selected_wires() const
 std::vector<RTLIL::Cell*> RTLIL::Module::selected_cells() const
 {
 	std::vector<RTLIL::Cell*> result;
-	result.reserve(wires_.size());
+	result.reserve(cells_.size());
 	for (auto &it : cells_)
 		if (design->selected(this, it.second))
 			result.push_back(it.second);
@@ -3554,6 +3554,12 @@ bool RTLIL::SigSpec::operator ==(const RTLIL::SigSpec &other) const
 	if (width_ != other.width_)
 		return false;
 
+	// Without this, SigSpec() == SigSpec(State::S0, 0) will fail
+	//   since the RHS will contain one SigChunk of width 0 causing
+	//   the size check below to fail
+	if (width_ == 0)
+		return true;
+
 	pack();
 	other.pack();
 
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index c08653b65..e5b24cc02 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -609,8 +609,11 @@ struct RTLIL::Const
 	std::string decode_string() const;
 
 	inline int size() const { return bits.size(); }
+	inline bool empty() const { return bits.empty(); }
 	inline RTLIL::State &operator[](int index) { return bits.at(index); }
 	inline const RTLIL::State &operator[](int index) const { return bits.at(index); }
+	inline decltype(bits)::iterator begin() { return bits.begin(); }
+	inline decltype(bits)::iterator end() { return bits.end(); }
 
 	bool is_fully_zero() const;
 	bool is_fully_ones() const;
diff --git a/kernel/yosys.h b/kernel/yosys.h
index a80cb00b4..179bfe07a 100644
--- a/kernel/yosys.h
+++ b/kernel/yosys.h
@@ -210,6 +210,7 @@ namespace RTLIL {
 	struct Module;
 	struct Design;
 	struct Monitor;
+	enum State : unsigned char;
 }
 
 namespace AST {