aboutsummaryrefslogtreecommitdiffstats
path: root/kernel
diff options
context:
space:
mode:
authorMarcelina Koƛcielnicka <mwk@0x04.net>2021-07-11 23:57:53 +0200
committerMarcelina Koƛcielnicka <mwk@0x04.net>2021-07-12 00:47:34 +0200
commit009940f56ca71cc8655a13a514371eb5757b96ca (patch)
tree8b194a81a92590973eb662c1207a876d010b2966 /kernel
parent726fabd65e51c7a15a2a2dc24d3b99426ef43ad2 (diff)
downloadyosys-009940f56ca71cc8655a13a514371eb5757b96ca.tar.gz
yosys-009940f56ca71cc8655a13a514371eb5757b96ca.tar.bz2
yosys-009940f56ca71cc8655a13a514371eb5757b96ca.zip
rtlil: Make Process handling more uniform with Cell and Wire.
- add a backlink to module from Process - make constructor and destructor protected, expose Module functions to add and remove processes
Diffstat (limited to 'kernel')
-rw-r--r--kernel/rtlil.cc32
-rw-r--r--kernel/rtlil.h16
-rw-r--r--kernel/yosys.h3
3 files changed, 48 insertions, 3 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index b7bef723f..21ee15ac5 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1839,6 +1839,14 @@ void RTLIL::Module::add(RTLIL::Cell *cell)
cell->module = this;
}
+void RTLIL::Module::add(RTLIL::Process *process)
+{
+ log_assert(!process->name.empty());
+ log_assert(count_id(process->name) == 0);
+ processes[process->name] = process;
+ process->module = this;
+}
+
void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
{
log_assert(refcount_wires_ == 0);
@@ -1895,6 +1903,13 @@ void RTLIL::Module::remove(RTLIL::Cell *cell)
delete cell;
}
+void RTLIL::Module::remove(RTLIL::Process *process)
+{
+ log_assert(processes.count(process->name) != 0);
+ processes.erase(process->name);
+ delete process;
+}
+
void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)
{
log_assert(wires_[wire->name] == wire);
@@ -2120,11 +2135,19 @@ RTLIL::Memory *RTLIL::Module::addMemory(RTLIL::IdString name, const RTLIL::Memor
return mem;
}
+RTLIL::Process *RTLIL::Module::addProcess(RTLIL::IdString name)
+{
+ RTLIL::Process *proc = new RTLIL::Process;
+ proc->name = name;
+ add(proc);
+ return proc;
+}
+
RTLIL::Process *RTLIL::Module::addProcess(RTLIL::IdString name, const RTLIL::Process *other)
{
RTLIL::Process *proc = other->clone();
proc->name = name;
- processes[name] = proc;
+ add(proc);
return proc;
}
@@ -2920,6 +2943,13 @@ RTLIL::Memory::Memory()
#endif
}
+RTLIL::Process::Process() : module(nullptr)
+{
+ static unsigned int hashidx_count = 123456789;
+ hashidx_count = mkhash_xorshift(hashidx_count);
+ hashidx_ = hashidx_count;
+}
+
RTLIL::Cell::Cell() : module(nullptr)
{
static unsigned int hashidx_count = 123456789;
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index d876d7831..dc0d5234b 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -1129,6 +1129,7 @@ struct RTLIL::Module : public RTLIL::AttrObject
protected:
void add(RTLIL::Wire *wire);
void add(RTLIL::Cell *cell);
+ void add(RTLIL::Process *process);
public:
RTLIL::Design *design;
@@ -1209,6 +1210,7 @@ public:
// Removing wires is expensive. If you have to remove wires, remove them all at once.
void remove(const pool<RTLIL::Wire*> &wires);
void remove(RTLIL::Cell *cell);
+ void remove(RTLIL::Process *process);
void rename(RTLIL::Wire *wire, RTLIL::IdString new_name);
void rename(RTLIL::Cell *cell, RTLIL::IdString new_name);
@@ -1228,6 +1230,7 @@ public:
RTLIL::Memory *addMemory(RTLIL::IdString name, const RTLIL::Memory *other);
+ RTLIL::Process *addProcess(RTLIL::IdString name);
RTLIL::Process *addProcess(RTLIL::IdString name, const RTLIL::Process *other);
// The add* methods create a cell and return the created cell. All signals must exist in advance.
@@ -1581,12 +1584,21 @@ struct RTLIL::SyncRule
struct RTLIL::Process : public RTLIL::AttrObject
{
+ unsigned int hashidx_;
+ unsigned int hash() const { return hashidx_; }
+
+protected:
+ // use module->addProcess() and module->remove() to create or destroy processes
+ friend struct RTLIL::Module;
+ Process();
+ ~Process();
+
+public:
RTLIL::IdString name;
+ RTLIL::Module *module;
RTLIL::CaseRule root_case;
std::vector<RTLIL::SyncRule*> syncs;
- ~Process();
-
template<typename T> void rewrite_sigspecs(T &functor);
template<typename T> void rewrite_sigspecs2(T &functor);
RTLIL::Process *clone() const;
diff --git a/kernel/yosys.h b/kernel/yosys.h
index 120311a6f..013c3308f 100644
--- a/kernel/yosys.h
+++ b/kernel/yosys.h
@@ -222,6 +222,7 @@ namespace RTLIL {
struct Wire;
struct Cell;
struct Memory;
+ struct Process;
struct Module;
struct Design;
struct Monitor;
@@ -245,6 +246,7 @@ namespace hashlib {
template<> struct hash_ops<RTLIL::Wire*> : hash_obj_ops {};
template<> struct hash_ops<RTLIL::Cell*> : hash_obj_ops {};
template<> struct hash_ops<RTLIL::Memory*> : hash_obj_ops {};
+ template<> struct hash_ops<RTLIL::Process*> : hash_obj_ops {};
template<> struct hash_ops<RTLIL::Module*> : hash_obj_ops {};
template<> struct hash_ops<RTLIL::Design*> : hash_obj_ops {};
template<> struct hash_ops<RTLIL::Monitor*> : hash_obj_ops {};
@@ -253,6 +255,7 @@ namespace hashlib {
template<> struct hash_ops<const RTLIL::Wire*> : hash_obj_ops {};
template<> struct hash_ops<const RTLIL::Cell*> : hash_obj_ops {};
template<> struct hash_ops<const RTLIL::Memory*> : hash_obj_ops {};
+ template<> struct hash_ops<const RTLIL::Process*> : hash_obj_ops {};
template<> struct hash_ops<const RTLIL::Module*> : hash_obj_ops {};
template<> struct hash_ops<const RTLIL::Design*> : hash_obj_ops {};
template<> struct hash_ops<const RTLIL::Monitor*> : hash_obj_ops {};