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| author | Sahand Kashani <sahand.kashani@gmail.com> | 2020-04-08 23:50:37 +0200 |
|---|---|---|
| committer | Sahand Kashani <sahand.kashani@gmail.com> | 2020-04-08 23:50:37 +0200 |
| commit | 9edf8869c18951ec2b75f074065f073da3253244 (patch) | |
| tree | 09fba95ba6d3f93ecab828c84b9ff3f74160d7b9 /kernel/timinginfo.h | |
| parent | 820e3d1dad4f484f9646588f79b73b21b495e3d8 (diff) | |
| parent | 5f649fc19d5cef76a634572ad0a493f1d2fd6306 (diff) | |
| download | yosys-9edf8869c18951ec2b75f074065f073da3253244.tar.gz yosys-9edf8869c18951ec2b75f074065f073da3253244.tar.bz2 yosys-9edf8869c18951ec2b75f074065f073da3253244.zip | |
Merge branch 'master' of github.com:YosysHQ/yosys into firrtl_backend_fileinfo
Diffstat (limited to 'kernel/timinginfo.h')
| -rw-r--r-- | kernel/timinginfo.h | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/kernel/timinginfo.h b/kernel/timinginfo.h index 4b77c02e8..fb4e0930d 100644 --- a/kernel/timinginfo.h +++ b/kernel/timinginfo.h @@ -82,20 +82,20 @@ struct TimingInfo for (auto cell : module->cells()) { if (cell->type == ID($specify2)) { - auto src = cell->getPort(ID(SRC)); - auto dst = cell->getPort(ID(DST)); + auto src = cell->getPort(ID::SRC); + auto dst = cell->getPort(ID::DST); for (const auto &c : src.chunks()) if (!c.wire->port_input) log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src)); for (const auto &c : dst.chunks()) if (!c.wire->port_output) log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", log_id(module), log_id(cell), log_signal(dst)); - int rise_max = cell->getParam(ID(T_RISE_MAX)).as_int(); - int fall_max = cell->getParam(ID(T_FALL_MAX)).as_int(); + int rise_max = cell->getParam(ID::T_RISE_MAX).as_int(); + int fall_max = cell->getParam(ID::T_FALL_MAX).as_int(); int max = std::max(rise_max,fall_max); if (max < 0) log_error("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0.\n", log_id(module), log_id(cell)); - if (cell->getParam(ID(FULL)).as_bool()) { + if (cell->getParam(ID::FULL).as_bool()) { for (const auto &s : src) for (const auto &d : dst) { auto r = t.comb.insert(BitBit(s,d)); @@ -117,16 +117,16 @@ struct TimingInfo } } else if (cell->type == ID($specify3)) { - auto src = cell->getPort(ID(SRC)); - auto dst = cell->getPort(ID(DST)); + auto src = cell->getPort(ID::SRC); + auto dst = cell->getPort(ID::DST); for (const auto &c : src.chunks()) if (!c.wire->port_input) log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src)); for (const auto &c : dst.chunks()) if (!c.wire->port_output) log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", log_id(module), log_id(cell), log_signal(dst)); - int rise_max = cell->getParam(ID(T_RISE_MAX)).as_int(); - int fall_max = cell->getParam(ID(T_FALL_MAX)).as_int(); + int rise_max = cell->getParam(ID::T_RISE_MAX).as_int(); + int fall_max = cell->getParam(ID::T_FALL_MAX).as_int(); int max = std::max(rise_max,fall_max); if (max < 0) log_warning("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell)); @@ -140,18 +140,18 @@ struct TimingInfo } } else if (cell->type == ID($specrule)) { - auto type = cell->getParam(ID(TYPE)).decode_string(); + auto type = cell->getParam(ID::TYPE).decode_string(); if (type != "$setup" && type != "$setuphold") continue; - auto src = cell->getPort(ID(SRC)); - auto dst = cell->getPort(ID(DST)); + auto src = cell->getPort(ID::SRC); + auto dst = cell->getPort(ID::DST); for (const auto &c : src.chunks()) if (!c.wire->port_input) log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src)); for (const auto &c : dst.chunks()) if (!c.wire->port_input) log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(dst)); - int max = cell->getParam(ID(T_LIMIT_MAX)).as_int(); + int max = cell->getParam(ID::T_LIMIT_MAX).as_int(); if (max < 0) log_warning("Module '%s' contains specify cell '%s' with T_LIMIT_MAX < 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell)); if (max <= 0) { |