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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-23 09:48:26 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-23 09:52:55 +0200 |
| commit | ec923652e2eb721aa16657e54a67666f855c3d65 (patch) | |
| tree | 934ce8ee55c3c58a1e2c11f19eec194665413906 /kernel/sigtools.h | |
| parent | a8d3a68971ccc4e47c54a906aae374a9a54b1415 (diff) | |
| download | yosys-ec923652e2eb721aa16657e54a67666f855c3d65.tar.gz yosys-ec923652e2eb721aa16657e54a67666f855c3d65.tar.bz2 yosys-ec923652e2eb721aa16657e54a67666f855c3d65.zip | |
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3
Diffstat (limited to 'kernel/sigtools.h')
| -rw-r--r-- | kernel/sigtools.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/kernel/sigtools.h b/kernel/sigtools.h index d011b0ef5..cd179ebf0 100644 --- a/kernel/sigtools.h +++ b/kernel/sigtools.h @@ -144,7 +144,7 @@ struct SigPool { RTLIL::SigSpec sig; for (auto &bit : bits) { - sig.append(RTLIL::SigSpec::grml(bit.first, bit.second)); + sig.append(RTLIL::SigSpec(bit.first, bit.second)); break; } return sig; @@ -154,7 +154,7 @@ struct SigPool { RTLIL::SigSpec sig; for (auto &bit : bits) - sig.append(RTLIL::SigSpec::grml(bit.first, bit.second)); + sig.append(RTLIL::SigSpec(bit.first, bit.second)); sig.sort_and_unify(); return sig; } |